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RISC-V: Add T-Head FMemIdx vendor extension

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T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
2022-06-28 17:44:57 +02:00
committed by Philipp Tomsich
parent 4041e11db3
commit f511f80fa3
10 changed files with 127 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
bfd/elfxx-riscv.c
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@ -1229,6 +1229,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0} {NULL, 0, 0, 0, 0}
@ -2403,6 +2404,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xtheadcmo"); return riscv_subset_supports (rps, "xtheadcmo");
case INSN_CLASS_XTHEADCONDMOV: case INSN_CLASS_XTHEADCONDMOV:
return riscv_subset_supports (rps, "xtheadcondmov"); return riscv_subset_supports (rps, "xtheadcondmov");
case INSN_CLASS_XTHEADFMEMIDX:
return riscv_subset_supports (rps, "xtheadfmemidx");
case INSN_CLASS_XTHEADMAC: case INSN_CLASS_XTHEADMAC:
return riscv_subset_supports (rps, "xtheadmac"); return riscv_subset_supports (rps, "xtheadmac");
case INSN_CLASS_XTHEADSYNC: case INSN_CLASS_XTHEADSYNC:
@ -2544,6 +2547,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xtheadcmo"; return "xtheadcmo";
case INSN_CLASS_XTHEADCONDMOV: case INSN_CLASS_XTHEADCONDMOV:
return "xtheadcondmov"; return "xtheadcondmov";
case INSN_CLASS_XTHEADFMEMIDX:
return "xtheadfmemidx";
case INSN_CLASS_XTHEADMAC: case INSN_CLASS_XTHEADMAC:
return "xtheadmac"; return "xtheadmac";
case INSN_CLASS_XTHEADSYNC: case INSN_CLASS_XTHEADSYNC:

5
gas/doc/c-riscv.texi
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@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
@item XTheadFMemIdx
The XTheadFMemIdx extension provides floating-point memory operations.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
@item XTheadMac @item XTheadMac
The XTheadMac extension provides multiply-accumulate instructions. The XTheadMac extension provides multiply-accumulate instructions.

3
gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d Normal file
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@ -0,0 +1,3 @@
#as: -march=rv64i_xtheadfmemidx
#source: x-thead-fmemidx-fail.s
#error_output: x-thead-fmemidx-fail.l

18
gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l Normal file
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@ -0,0 +1,18 @@
.*: Assembler messages:
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)
.*: Error: improper immediate value \(18446744073709551615\)
.*: Error: improper immediate value \(4\)

17
gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s Normal file
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@ -0,0 +1,17 @@
target:
th.flrd a0, a1, a2, -1
th.flrd a0, a1, a2, 4
th.flrw a0, a1, a2, -1
th.flrw a0, a1, a2, 4
th.flurd a0, a1, a2, -1
th.flurd a0, a1, a2, 4
th.flurw a0, a1, a2, -1
th.flurw a0, a1, a2, 4
th.fsrd a0, a1, a2, -1
th.fsrd a0, a1, a2, 4
th.fsrw a0, a1, a2, -1
th.fsrw a0, a1, a2, 4
th.fsurd a0, a1, a2, -1
th.fsurd a0, a1, a2, 4
th.fsurw a0, a1, a2, -1
th.fsurw a0, a1, a2, 4

25
gas/testsuite/gas/riscv/x-thead-fmemidx.d Normal file
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@ -0,0 +1,25 @@
#as: -march=rv64i_xtheadfmemidx
#source: x-thead-fmemidx.s
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3
[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0
[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3

17
gas/testsuite/gas/riscv/x-thead-fmemidx.s Normal file
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@ -0,0 +1,17 @@
target:
th.flrd a0, a1, a2, 0
th.flrd a0, a1, a2, 3
th.flrw a0, a1, a2, 0
th.flrw a0, a1, a2, 3
th.flurd a0, a1, a2, 0
th.flurd a0, a1, a2, 3
th.flurw a0, a1, a2, 0
th.flurw a0, a1, a2, 3
th.fsrd a0, a1, a2, 0
th.fsrd a0, a1, a2, 3
th.fsrw a0, a1, a2, 0
th.fsrw a0, a1, a2, 3
th.fsurd a0, a1, a2, 0
th.fsurd a0, a1, a2, 3
th.fsurw a0, a1, a2, 0
th.fsurw a0, a1, a2, 3

26
include/opcode/riscv-opc.h
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@ -2186,6 +2186,23 @@
#define MASK_TH_MVEQZ 0xfe00707f #define MASK_TH_MVEQZ 0xfe00707f
#define MATCH_TH_MVNEZ 0x4200100b #define MATCH_TH_MVNEZ 0x4200100b
#define MASK_TH_MVNEZ 0xfe00707f #define MASK_TH_MVNEZ 0xfe00707f
/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
#define MATCH_TH_FLRD 0x6000600b
#define MASK_TH_FLRD 0xf800707f
#define MATCH_TH_FLRW 0x4000600b
#define MASK_TH_FLRW 0xf800707f
#define MATCH_TH_FLURD 0x7000600b
#define MASK_TH_FLURD 0xf800707f
#define MATCH_TH_FLURW 0x5000600b
#define MASK_TH_FLURW 0xf800707f
#define MATCH_TH_FSRD 0x6000700b
#define MASK_TH_FSRD 0xf800707f
#define MATCH_TH_FSRW 0x4000700b
#define MASK_TH_FSRW 0xf800707f
#define MATCH_TH_FSURD 0x7000700b
#define MASK_TH_FSURD 0xf800707f
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadMac instructions. */ /* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b #define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f #define MASK_TH_MULA 0xfe00707f
@ -2988,6 +3005,15 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
/* Vendor-specific (T-Head) XTheadCondMov instructions. */ /* Vendor-specific (T-Head) XTheadCondMov instructions. */
DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ)
DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ)
/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
DECLARE_INSN(th_flrd, MATCH_TH_FLRD, MASK_TH_FLRD)
DECLARE_INSN(th_flrw, MATCH_TH_FLRW, MASK_TH_FLRW)
DECLARE_INSN(th_flurd, MATCH_TH_FLURD, MASK_TH_FLURD)
DECLARE_INSN(th_flurw, MATCH_TH_FLURW, MASK_TH_FLURW)
DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD)
DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW)
DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD)
DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
/* Vendor-specific (T-Head) XTheadMac instructions. */ /* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)

1
include/opcode/riscv.h
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@ -420,6 +420,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADBS,
INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADFMEMIDX,
INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADSYNC,
}; };

10
opcodes/riscv-opc.c
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@ -1871,6 +1871,16 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0},
{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0},
{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0},
{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0},
{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0},
{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadMac instructions. */ /* Vendor-specific (T-Head) XTheadMac instructions. */
{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0},
{"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, {"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0},