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Power10 vector integer multiply, divide, modulo insns
opcodes/ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. gas/ * testsuite/gas/ppc/vec_mul.s, * testsuite/gas/ppc/vec_mul.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
This commit is contained in:
Alan Modra
@ -1,3 +1,9 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/vec_mul.s,
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* testsuite/gas/ppc/vec_mul.d: New test.
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* testsuite/gas/ppc/ppc.exp: Run it.
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2020-05-11 Peter Bergner <bergner@linux.ibm.com>
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2020-05-11 Peter Bergner <bergner@linux.ibm.com>
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* testsuite/gas/ppc/byte_rev.d,
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* testsuite/gas/ppc/byte_rev.d,
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@ -132,3 +132,4 @@ if { [supports_ppc64] } then {
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run_dump_test "prefix-reloc"
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run_dump_test "prefix-reloc"
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}
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}
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run_dump_test "byte_rev"
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run_dump_test "byte_rev"
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run_dump_test "vec_mul"
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27
gas/testsuite/gas/ppc/vec_mul.d
Normal file
27
gas/testsuite/gas/ppc/vec_mul.d
Normal file
@ -0,0 +1,27 @@
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#as: -mpower10
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#objdump: -dr -Mpower10
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#name: vector integer mul/div/mod
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.*
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Disassembly of section \.text:
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0+0 <_start>:
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.*: (10 22 1b 89|89 1b 22 10) vmulhsw v1,v2,v3
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.*: (10 85 32 89|89 32 85 10) vmulhuw v4,v5,v6
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.*: (10 e8 4b c9|c9 4b e8 10) vmulhsd v7,v8,v9
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.*: (11 4b 62 c9|c9 62 4b 11) vmulhud v10,v11,v12
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.*: (11 ae 79 c9|c9 79 ae 11) vmulld v13,v14,v15
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.*: (12 11 91 8b|8b 91 11 12) vdivsw v16,v17,v18
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.*: (12 74 a8 8b|8b a8 74 12) vdivuw v19,v20,v21
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.*: (12 d7 c3 8b|8b c3 d7 12) vdivesw v22,v23,v24
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.*: (13 3a da 8b|8b da 3a 13) vdiveuw v25,v26,v27
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.*: (13 9d f1 cb|cb f1 9d 13) vdivsd v28,v29,v30
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.*: (13 e0 08 cb|cb 08 e0 13) vdivud v31,v0,v1
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.*: (10 43 23 cb|cb 23 43 10) vdivesd v2,v3,v4
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.*: (10 a6 3a cb|cb 3a a6 10) vdiveud v5,v6,v7
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.*: (11 09 57 8b|8b 57 09 11) vmodsw v8,v9,v10
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.*: (11 6c 6e 8b|8b 6e 6c 11) vmoduw v11,v12,v13
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.*: (11 cf 87 cb|cb 87 cf 11) vmodsd v14,v15,v16
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.*: (12 32 9e cb|cb 9e 32 12) vmodud v17,v18,v19
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19
gas/testsuite/gas/ppc/vec_mul.s
Normal file
19
gas/testsuite/gas/ppc/vec_mul.s
Normal file
@ -0,0 +1,19 @@
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.text
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_start:
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vmulhsw 1,2,3
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vmulhuw 4,5,6
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vmulhsd 7,8,9
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vmulhud 10,11,12
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vmulld 13,14,15
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vdivsw 16,17,18
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vdivuw 19,20,21
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vdivesw 22,23,24
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vdiveuw 25,26,27
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vdivsd 28,29,30
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vdivud 31,0,1
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vdivesd 2,3,4
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vdiveud 5,6,7
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vmodsw 8,9,10
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vmoduw 11,12,13
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vmodsd 14,15,16
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vmodud 17,18,19
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@ -1,3 +1,9 @@
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2020-05-11 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
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vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
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vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
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2020-05-11 Peter Bergner <bergner@linux.ibm.com>
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2020-05-11 Peter Bergner <bergner@linux.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
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* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
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@ -3983,6 +3983,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
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{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
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@ -3996,6 +3997,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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@ -4036,6 +4038,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
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||||||
{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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@ -4044,7 +4047,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
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||||||
{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
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{"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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||||||
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{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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||||||
{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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@ -4134,9 +4139,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
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{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
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||||||
{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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||||||
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{"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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||||||
{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
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{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
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||||||
{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
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{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
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@ -4193,9 +4200,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
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{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
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||||||
{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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||||||
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{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
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||||||
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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||||||
{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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||||||
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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||||||
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{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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||||||
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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||||||
{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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@ -4331,8 +4340,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
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{"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}},
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||||||
{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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||||||
{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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||||||
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{"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}},
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||||||
{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
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{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
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||||||
{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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||||||
{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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||||||
@ -4341,8 +4352,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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||||||
{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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||||||
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{"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}},
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||||||
{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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||||||
{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
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||||||
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{"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}},
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||||||
{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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||||||
{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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||||||
{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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||||||
@ -4632,6 +4645,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||||||
{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||||
|
{"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||||
{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||||
{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
|
{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
|
||||||
{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
|
{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
|
||||||
@ -4640,6 +4654,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||||||
{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||||
{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
|
{"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||||
{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
|
{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
|
||||||
{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||||
{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
|
{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
|
||||||
@ -4671,6 +4686,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||||||
{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
|
||||||
|
{"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||||
{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||||
{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
|
{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
|
||||||
{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||||
@ -4681,6 +4697,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||||||
{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
|
||||||
{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
|
||||||
|
{"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}},
|
||||||
{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||||
{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||||
{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
|
||||||
|
|||||||
Reference in New Issue
Block a user