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MIPS Documentation fixes
gas/ * doc/as.texinfo: Update the MIPS FP ABI descriptions. * doc/c-mips.texi: Spell check and correct throughout.
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@ -1,3 +1,8 @@
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2014-10-22 Matthew Fortune <matthew.fortune@imgtec.com>
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* doc/as.texinfo: Update the MIPS FP ABI descriptions.
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* doc/c-mips.texi: Spell check and correct throughout.
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2014-10-21 Maciej W. Rozycki <macro@codesourcery.com>
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2014-10-21 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (s_insn): Set file options.
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* config/tc-mips.c (s_insn): Set file options.
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@ -7030,16 +7030,27 @@ The floating-point ABI used by this object file. The value will be:
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@item
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@item
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0 for files not affected by the floating-point ABI.
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0 for files not affected by the floating-point ABI.
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@item
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@item
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1 for files using the hardware floating-point with a standard double-precision
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1 for files using the hardware floating-point ABI with a standard
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FPU.
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double-precision FPU.
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@item
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@item
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2 for files using the hardware floating-point ABI with a single-precision FPU.
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2 for files using the hardware floating-point ABI with a single-precision FPU.
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@item
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@item
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3 for files using the software floating-point ABI.
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3 for files using the software floating-point ABI.
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@item
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@item
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4 for files using the hardware floating-point ABI with 64-bit wide
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4 for files using the deprecated hardware floating-point ABI which used 64-bit
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double-precision floating-point registers and 32-bit wide general
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floating-point registers, 32-bit general-purpose registers and increased the
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purpose registers.
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number of callee-saved floating-point registers.
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@item
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5 for files using the hardware floating-point ABI with a double-precision FPU
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with either 32-bit or 64-bit floating-point registers and 32-bit
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general-purpose registers.
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@item
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6 for files using the hardware floating-point ABI with 64-bit floating-point
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registers and 32-bit general-purpose registers.
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@item
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7 for files using the hardware floating-point ABI with 64-bit floating-point
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registers, 32-bit general-purpose registers and a rule that forbids the
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direct use of odd-numbered single-precision floating-point registers.
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@end itemize
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@end itemize
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@end table
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@end table
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@ -769,9 +769,9 @@ The @code{.global} and @code{.globl} directives supported by
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region of data not code. This means that, for example, any
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region of data not code. This means that, for example, any
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instructions following such a symbol will not be disassembled by
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instructions following such a symbol will not be disassembled by
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@code{objdump} as it will regard them as data. To change this
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@code{objdump} as it will regard them as data. To change this
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behaviour an optional section name can be placed after the symbol name
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behavior an optional section name can be placed after the symbol name
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in the @code{.global} directive. If this section exists and is known
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in the @code{.global} directive. If this section exists and is known
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to be a code section, then the symbol will be marked as poiting at
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to be a code section, then the symbol will be marked as pointing at
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code not data. Ie the syntax for the directive is:
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code not data. Ie the syntax for the directive is:
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@code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
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@code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
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@ -840,8 +840,8 @@ pass all floating-point data in general-purpose registers.
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@item 4 - Deprecated
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@item 4 - Deprecated
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This variant existed as an initial attempt at supporting 64-bit wide
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This variant existed as an initial attempt at supporting 64-bit wide
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floating-point registers for O32 ABI on a MIPS32r2 cpu. This has been
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floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
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superceded by 5, 6 and 7.
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superseded by 5, 6 and 7.
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@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
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@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
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This variant is used by 32-bit ABIs to indicate that the floating-point
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This variant is used by 32-bit ABIs to indicate that the floating-point
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@ -998,7 +998,7 @@ Release 1 instructions from being accepted.
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@kindex @code{.set nodspr2}
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@kindex @code{.set nodspr2}
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The directive @code{.set dspr2} makes the assembler accept instructions
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The directive @code{.set dspr2} makes the assembler accept instructions
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from the DSP Release 2 Application Specific Extension from that point
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from the DSP Release 2 Application Specific Extension from that point
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on in the assembly. This dirctive implies @code{.set dsp}. The
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on in the assembly. This directive implies @code{.set dsp}. The
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@code{.set nodspr2} directive prevents DSP Release 2 instructions from
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@code{.set nodspr2} directive prevents DSP Release 2 instructions from
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being accepted.
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being accepted.
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