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o Implement generic halt/restart/abort module.
Use in tic80 and d30v simulators. o Add signal hook to sim-core module
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@ -69,39 +69,4 @@ extern void engine_init
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(SIM_DESC sd);
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/* Mechanisms for stopping/restarting the simulation.
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A non NULL CPU argument designates the processor that is initiating
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the halt. After the simulation has stopped that processor should
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be marked as the last one active */
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extern void engine_error
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(SIM_DESC sd,
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sim_cpu *cpu,
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instruction_address cia,
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const char *fmt,
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...);
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extern void engine_halt
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(SIM_DESC sd,
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sim_cpu *cpu,
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instruction_address cia,
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enum sim_stop reason,
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int siggnal);
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extern void engine_restart
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(SIM_DESC sd,
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sim_cpu *cpu,
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instruction_address cia);
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/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
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thing (others later) */
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extern void engine_run_until_stop
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(SIM_DESC sd,
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volatile int *keep_running);
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extern void engine_step
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(SIM_DESC sd);
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#endif
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