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o Implement generic halt/restart/abort module.

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Use in tic80 and d30v simulators.
o	Add signal hook to sim-core module
This commit is contained in:
Andrew Cagney
1997-05-19 03:42:33 +00:00
parent 11ab132f16
commit f03b093cd3
18 changed files with 1415 additions and 377 deletions
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21
sim/tic80/interp.c
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@ -36,16 +36,8 @@
#endif
#endif
void
engine_init (SIM_DESC sd)
{
memset (&STATE_CPU (sd, 0)->reg, 0, sizeof STATE_CPU (sd, 0)->reg);
memset (&STATE_CPU (sd, 0)->cia, 0, sizeof STATE_CPU (sd, 0)->cia);
CPU_STATE (STATE_CPU (sd, 0)) = sd;
}
/* Mechanisms for stopping/restarting the simulation */
#if 0
void
engine_error (SIM_DESC sd,
@ -59,13 +51,7 @@ engine_error (SIM_DESC sd,
sim_io_evprintf (sd, fmt, ap);
va_end (ap);
if (sd->halt_ok)
{
sim_io_eprintf (sd, "\n");
engine_halt (sd, cpu, cia, sim_stopped, SIGABRT);
}
else
sim_io_error (sd, " - aborting simulation");
sim_halt (sd, cpu, NULL, cia, sim_stopped, SIGABRT);
}
void
@ -139,3 +125,6 @@ engine_step (SIM_DESC sd)
engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
}
}
#endif