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x86: Correct xsusldtrk mnemonic

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The correct mnemonic is xsusldtrk, not xsuspldtrk.

gas/

	PR gas/26115
	* testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
	xsusldtrk.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.

opcodes/

	PR gas/26115
	* i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
2020-06-14 05:18:35 -07:00
parent 83015056b2
commit efe30057d2
8 changed files with 22 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26115
* testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
xsusldtrk.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.
2020-06-12 Nelson Chu <nelson.chu@sifive.com> 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.

2
gas/testsuite/gas/i386/tsxldtrk.d
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@ -8,6 +8,6 @@
Disassembly of section \.text: Disassembly of section \.text:
0+ <_start>: 0+ <_start>:
+[a-f0-9]+: f2 0f 01 e8 xsuspldtrk[ ]* +[a-f0-9]+: f2 0f 01 e8 xsusldtrk[ ]*
+[a-f0-9]+: f2 0f 01 e9 xresldtrk[ ]* +[a-f0-9]+: f2 0f 01 e9 xresldtrk[ ]*
#pass #pass

2
gas/testsuite/gas/i386/tsxldtrk.s
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@ -2,5 +2,5 @@
.text .text
_start: _start:
xsuspldtrk xsusldtrk
xresldtrk xresldtrk

2
gas/testsuite/gas/i386/x86-64-tsxldtrk.d
View File

@ -8,6 +8,6 @@
Disassembly of section \.text: Disassembly of section \.text:
0+ <_start>: 0+ <_start>:
+[a-f0-9]+: f2 0f 01 e8 xsuspldtrk[ ]* +[a-f0-9]+: f2 0f 01 e8 xsusldtrk[ ]*
+[a-f0-9]+: f2 0f 01 e9 xresldtrk[ ]* +[a-f0-9]+: f2 0f 01 e9 xresldtrk[ ]*
#pass #pass

7
opcodes/ChangeLog
View File

@ -1,3 +1,10 @@
2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26115
* i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
2020-06-12 Nelson Chu <nelson.chu@sifive.com> 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9. * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.

2
opcodes/i386-dis.c
View File

@ -3591,7 +3591,7 @@ static const struct dis386 prefix_table[][4] = {
{ "serialize", { Skip_MODRM }, PREFIX_OPCODE }, { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
{ Bad_Opcode }, { Bad_Opcode },
{ "xsuspldtrk", { Skip_MODRM }, PREFIX_OPCODE }, { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
}, },
/* PREFIX_0F01_REG_5_MOD_3_RM_1 */ /* PREFIX_0F01_REG_5_MOD_3_RM_1 */

2
opcodes/i386-opc.tbl
View File

@ -4085,7 +4085,7 @@ serialize, 0, 0x0f01e8, None, 3, CpuSERIALIZE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
// TSXLDTRK instructions. // TSXLDTRK instructions.
xsuspldtrk, 0, 0xf20f01e8, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } xsusldtrk, 0, 0xf20f01e8, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
xresldtrk, 0, 0xf20f01e9, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } xresldtrk, 0, 0xf20f01e9, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// TSXLDTRK instructions end. // TSXLDTRK instructions end.

2
opcodes/i386-tbl.h
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@ -59404,7 +59404,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } }, 0, 0, 0, 0, 0, 0 } } } },
{ "xsuspldtrk", 0xf20f01e8, None, 3, 0, { "xsusldtrk", 0xf20f01e8, None, 3, 0,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,