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Tidy up AArch64 simulator code.

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* cpustate.c: Remove space after asterisk in function parameters.
	* decode.h (greg): Delete unused function.
	(vreg, shift, extension, scaling, writeback, condcode): Likewise.
	* simulator.c: Use INSTR macro in more places.
	(HALT_NYI): Use sim_io_eprintf in place of fprintf.
	Remove extraneous whitespace.
This commit is contained in:
Nick Clifton
2016-03-29 11:34:22 +01:00
parent ed3056ebdb
commit ef0d8ffc45
4 changed files with 1412 additions and 1468 deletions
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9
sim/aarch64/ChangeLog
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@ -1,3 +1,12 @@
2016-03-29 Nick Clifton <nickc@redhat.com>
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
2016-03-23 Nick Clifton <nickc@redhat.com> 2016-03-23 Nick Clifton <nickc@redhat.com>
* cpustate.c (aarch64_get_FP_half): New function. Read a vector * cpustate.c (aarch64_get_FP_half): New function. Read a vector

14
sim/aarch64/cpustate.c
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@ -470,25 +470,25 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
while (0) while (0)
void void
aarch64_set_vec_u64 (sim_cpu * cpu, VReg reg, unsigned element, uint64_t val) aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
{ {
SET_VEC_ELEMENT (reg, element, val, v, "%16lx"); SET_VEC_ELEMENT (reg, element, val, v, "%16lx");
} }
void void
aarch64_set_vec_u32 (sim_cpu * cpu, VReg reg, unsigned element, uint32_t val) aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
{ {
SET_VEC_ELEMENT (reg, element, val, w, "%8x"); SET_VEC_ELEMENT (reg, element, val, w, "%8x");
} }
void void
aarch64_set_vec_u16 (sim_cpu * cpu, VReg reg, unsigned element, uint16_t val) aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
{ {
SET_VEC_ELEMENT (reg, element, val, h, "%4x"); SET_VEC_ELEMENT (reg, element, val, h, "%4x");
} }
void void
aarch64_set_vec_u8 (sim_cpu * cpu, VReg reg, unsigned element, uint8_t val) aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
{ {
SET_VEC_ELEMENT (reg, element, val, b, "%x"); SET_VEC_ELEMENT (reg, element, val, b, "%x");
} }
@ -573,19 +573,19 @@ aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
} }
uint64_t uint64_t
aarch64_get_thread_id (sim_cpu * cpu) aarch64_get_thread_id (sim_cpu *cpu)
{ {
return cpu->tpidr; return cpu->tpidr;
} }
uint32_t uint32_t
aarch64_get_FPCR (sim_cpu * cpu) aarch64_get_FPCR (sim_cpu *cpu)
{ {
return cpu->FPCR; return cpu->FPCR;
} }
void void
aarch64_set_FPCR (sim_cpu * cpu, uint32_t val) aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
{ {
if (cpu->FPCR != val) if (cpu->FPCR != val)
TRACE_REGISTER (cpu, TRACE_REGISTER (cpu,

44
sim/aarch64/decode.h
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@ -177,20 +177,6 @@ pickbits64 (uint64_t val, int hi, int lo)
return pick64 (val, hi, lo) >> lo; return pick64 (val, hi, lo) >> lo;
} }
/* Decode registers, immediates and constants of various types. */
static inline GReg
greg (uint32_t val, int lo)
{
return (GReg) pickbits32 (val, lo + 4, lo);
}
static inline VReg
vreg (uint32_t val, int lo)
{
return (VReg) pickbits32 (val, lo + 4, lo);
}
static inline uint32_t static inline uint32_t
uimm (uint32_t val, int hi, int lo) uimm (uint32_t val, int hi, int lo)
{ {
@ -223,36 +209,6 @@ simm64 (uint64_t val, int hi, int lo)
return x.n >> (63 - hi + lo); return x.n >> (63 - hi + lo);
} }
static inline Shift
shift (uint32_t val, int lo)
{
return (Shift) pickbits32 (val, lo + 1, lo);
}
static inline Extension
extension (uint32_t val, int lo)
{
return (Extension) pickbits32 (val, lo + 2, lo);
}
static inline Scaling
scaling (uint32_t val, int lo)
{
return (Scaling) pickbits32 (val, lo, lo);
}
static inline WriteBack
writeback (uint32_t val, int lo)
{
return (WriteBack) pickbits32 (val, lo, lo);
}
static inline CondCode
condcode (uint32_t val, int lo)
{
return (CondCode) pickbits32 (val, lo + 3, lo);
}
/* Operation decode. /* Operation decode.
Bits [28,24] are the primary dispatch vector. */ Bits [28,24] are the primary dispatch vector. */

2765
sim/aarch64/simulator.c
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