mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-21 10:34:21 +08:00
2001-06-28 Eric Christopher <echristo@redhat.com>
H.J. Lu <hjl@gnu.org> * config/tc-mips.c (mips_arch): New. Use mips_arch instead of mips_cpu for the ISA selection. (md_longopts): Add OPTION_MARCH and OPTION_MTUNE. (md_parse_option): Handle OPTION_MARCH and OPTION_MTUNE. (mips_tune): New. Use mips_tune for scheduling and optimization issues. (append_insn): Use mips_tune and mips_arch. (macro_build): Ditto. (mips_ip): Ditto. (md_begin): Handle mips_arch, mips_tune and mips_cpu. For backwards compatability mips_cpu generates arch and tune. (md_show_usage): Document new behavior. * doc/c-mips.texi (MIPS Opts): Document -march and -mtune. Deprecate -mcpu. * NEWS: Update. 2001-06-28 Eric Christopher <echristo@redhat.com> * gas/mips/usd.d: Change for march/mtune. * gas/mips/ulh-xgot.d: Ditto. * gas/mips/uld.d: Ditto. * gas/mips/trunc.d: Ditto. * gas/mips/rol.d: Ditto. * gas/mips/nodelay.d: Ditto. * gas/mips/mul.d: Ditto. * gas/mips/mul-ilocks.d: Ditto. * gas/mips/trap20.d: Ditto. * gas/mips/mips4.d: Ditto. * gas/mips/mips16.d: Ditto. * gas/mips/lif-xgot.d: Ditto. * gas/mips/lif-svr4pic.d: Ditto. * gas/mips/ld-xgot.d: Ditto. * gas/mips/ld-svr4pic.d: Ditto. * gas/mips/ld-ilocks-addr32.d: Ditto. * gas/mips/lb-xgot.d: Ditto. * gas/mips/jal-xgot.d: Ditto. * gas/mips/jal-svr4pic.d: Ditto. * gas/mips/delay.d: Ditto. * gas/mips/lb-xgot-ilocks.d: Ditto. * gas/mips/div.d: Ditto. * gas/mips/break20.d: Ditto. * gas/mips/delay.d: Ditto. * gas/mips/elf_e_flags3.d: Ditto. * gas/mips/elf_e_flags4.d: Ditto. * gas/mips/lineno.d: Ditto. * gas/mips/mips16.d: Ditto. * gas/mips/mips4.d: Ditto. * gas/mips/mips4010.d: Ditto. * gas/mips/mips4650.d: Ditto.
This commit is contained in:
Eric Christopher
@ -1,3 +1,24 @@
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2001-06-28 Eric Christopher <echristo@redhat.com>
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H.J. Lu <hjl@gnu.org>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>* config/tc-mips.c (mips_arch): New. Use mips_arch instead
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>of mips_cpu for the ISA selection.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(md_longopts): Add OPTION_MARCH and OPTION_MTUNE.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(md_parse_option): Handle OPTION_MARCH and OPTION_MTUNE.
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(mips_tune): New. Use mips_tune for scheduling and optimization
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issues.
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(append_insn): Use mips_tune and mips_arch.
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(macro_build): Ditto.
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(mips_ip): Ditto.
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(md_begin): Handle mips_arch, mips_tune and mips_cpu. For
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backwards compatability mips_cpu generates arch and tune.
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(md_show_usage): Document new behavior.
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* doc/c-mips.texi (MIPS Opts): Document -march and -mtune.
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Deprecate -mcpu.
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* NEWS: Update.
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2001-06-27 Nick Clifton <nickc@cambridge.redhat.com>
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* write.c (write_object_file): Do not set finalize_syms until
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3
gas/NEWS
3
gas/NEWS
@ -1,5 +1,8 @@
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-*- text -*-
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The MIPS assembler now accepts -march/-mtune. -mcpu has been deprecated
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but still works for compatability.
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The MIPS assembler no longer issues a warning by default when it
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generates a nop instruction from a macro. The new command line option
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-n will turn on the warning.
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@ -206,9 +206,16 @@ unsigned long mips_cprmask[4];
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/* MIPS ISA we are using for this output file. */
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static int file_mips_isa = ISA_UNKNOWN;
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/* The CPU type we are using for this output file. */
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/* The argument of the -mcpu= flag. Historical for code generation. */
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static int mips_cpu = CPU_UNKNOWN;
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/* The argument of the -march= flag. The architecture we are assembling. */
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static int mips_arch = CPU_UNKNOWN;
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/* The argument of the -mtune= flag. The architecture for which we
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are optimizing. */
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static int mips_tune = CPU_UNKNOWN;
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/* The argument of the -mabi= flag. */
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static char * mips_abi_string = 0;
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@ -246,44 +253,21 @@ static int mips_gp32 = 0;
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted.
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require nops to be inserted. */
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FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
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-mcpu=FOO schedules for FOO, but still produces code that meets the
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requirements of MIPS ISA I. For example, it won't generate any
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FOO-specific instructions, and it will still assume that any
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scheduling hazards described in MIPS ISA I are there, even if FOO
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has interlocks. -mFOO gives GCC permission to generate code that
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will only run on a FOO; it will generate FOO-specific instructions,
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and assume interlocks provided by a FOO.
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However, GAS currently doesn't make this distinction; before Jan 28
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1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
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assumptions. The GCC driver passes these flags through to GAS, so
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if GAS actually does anything that doesn't meet MIPS ISA I with
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-mFOO, then GCC's -mcpu=FOO flag isn't going to work.
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And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
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which seems senseless --- why generate code which will only run on
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a FOO, but schedule for something else?
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So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
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-- Jim Blandy <jimb@cygnus.com> */
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#define hilo_interlocks (mips_cpu == CPU_R4010 \
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#define hilo_interlocks (mips_arch == CPU_R4010 \
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)
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/* Whether the processor uses hardware interlocks to protect reads
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from the GPRs, and thus does not require nops to be inserted. */
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#define gpr_interlocks \
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(mips_opts.isa != ISA_MIPS1 \
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|| mips_cpu == CPU_R3900)
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|| mips_arch == CPU_R3900)
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/* As with other "interlocks" this is used by hardware that has FP
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(co-processor) interlocks. */
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/* Itbl support may require additional care here. */
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#define cop_interlocks (mips_cpu == CPU_R4300 \
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#define cop_interlocks (mips_arch == CPU_R4300 \
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)
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/* Is this a mfhi or mflo instruction? */
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@ -955,40 +939,56 @@ md_begin ()
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if (mips_opts.mips16 < 0)
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mips_opts.mips16 = target_cpu_had_mips16;
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/* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
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/* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
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specified on the command line, or some other value if one was.
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Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
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the command line, or will be set otherwise if one was. */
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if (mips_cpu != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
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if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
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{
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/* We have it all. There's nothing to do. */
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}
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else if (mips_cpu != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
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else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
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{
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/* We have CPU, we need ISA. */
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ci = mips_cpu_info_from_cpu (mips_cpu);
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/* We have ARCH, we need ISA. */
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ci = mips_cpu_info_from_cpu (mips_arch);
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assert (ci != NULL);
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mips_opts.isa = ci->isa;
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}
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else if (mips_cpu == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
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else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
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{
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/* We have ISA, we need default CPU. */
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/* We have ISA, we need default ARCH. */
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ci = mips_cpu_info_from_isa (mips_opts.isa);
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assert (ci != NULL);
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mips_cpu = ci->cpu;
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mips_arch = ci->cpu;
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}
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else if (mips_arch == CPU_UNKNOWN
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&& mips_opts.isa == ISA_UNKNOWN
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&& mips_cpu != CPU_UNKNOWN)
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{
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/* Historic -mcpu= option. Warn. */
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ci = mips_cpu_info_from_cpu (mips_cpu);
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assert (ci != NULL);
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mips_arch = ci->cpu;
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mips_tune = ci->cpu;
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mips_opts.isa = ci->isa;
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as_warn (_("The -mcpu option is deprecated. Please use -march and -mtune instead."));
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}
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else
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{
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/* We need to set both ISA and CPU from target cpu. */
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/* We need to set both ISA and ARCH from target cpu. */
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ci = mips_cpu_info_from_name (cpu);
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if (ci == NULL)
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ci = mips_cpu_info_from_cpu (CPU_R3000);
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assert (ci != NULL);
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mips_opts.isa = ci->isa;
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mips_cpu = ci->cpu;
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mips_arch = ci->cpu;
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}
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ci = mips_cpu_info_from_cpu (mips_cpu);
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if (mips_tune == CPU_UNKNOWN)
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mips_tune = mips_arch;
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ci = mips_cpu_info_from_cpu (mips_arch);
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assert (ci != NULL);
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mips_isa_from_cpu = ci->isa;
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@ -1019,7 +1019,7 @@ md_begin ()
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&& ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
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mips_32bitmode = 1;
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu))
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
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as_warn (_("Could not set architecture and machine"));
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file_mips_isa = mips_opts.isa;
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@ -1593,7 +1593,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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though the tx39's divide insns still do require the
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delay. */
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if (! (hilo_interlocks
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|| (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
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|| (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_LO)))
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nops += 2;
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@ -1615,7 +1615,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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insert a NOP. Some newer processors have interlocks.
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Also the note tx39's multiply above. */
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if (! (hilo_interlocks
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|| (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
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|| (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_HI)))
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nops += 2;
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@ -1654,11 +1654,11 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
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&& (pinfo & INSN_WRITE_LO)
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&& ! (hilo_interlocks
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|| (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))))
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|| (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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&& (pinfo & INSN_WRITE_HI)
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&& ! (hilo_interlocks
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|| (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))))
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|| (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
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prev_prev_nop = 1;
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else
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prev_prev_nop = 0;
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@ -2011,7 +2011,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE)))
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|| (! (hilo_interlocks
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|| (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))
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|| (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
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&& (prev_pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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@ -2496,9 +2496,9 @@ macro_build (place, counter, ep, name, fmt, va_alist)
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{
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if (strcmp (fmt, insn.insn_mo->args) == 0
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&& insn.insn_mo->pinfo != INSN_MACRO
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&& OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu,
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&& OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch,
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mips_gp32)
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&& (mips_cpu != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
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&& (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
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break;
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++insn.insn_mo;
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@ -4848,7 +4848,7 @@ macro (ip)
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lr = 1;
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goto ld;
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case M_LDC1_AB:
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if (mips_cpu == CPU_R4650)
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if (mips_arch == CPU_R4650)
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{
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as_bad (_("opcode not supported on this processor"));
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return;
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@ -4937,7 +4937,7 @@ macro (ip)
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s = "scd";
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goto st;
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case M_SDC1_AB:
|
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if (mips_cpu == CPU_R4650)
|
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if (mips_arch == CPU_R4650)
|
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{
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as_bad (_("opcode not supported on this processor"));
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return;
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@ -5425,7 +5425,7 @@ macro (ip)
|
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}
|
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case M_L_DOB:
|
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if (mips_cpu == CPU_R4650)
|
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if (mips_arch == CPU_R4650)
|
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{
|
||||
as_bad (_("opcode not supported on this processor"));
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return;
|
||||
@ -5466,7 +5466,7 @@ macro (ip)
|
||||
* But, the resulting address is the same after relocation so why
|
||||
* generate the extra instruction?
|
||||
*/
|
||||
if (mips_cpu == CPU_R4650)
|
||||
if (mips_arch == CPU_R4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
||||
@ -5484,7 +5484,7 @@ macro (ip)
|
||||
goto ldd_std;
|
||||
|
||||
case M_S_DAB:
|
||||
if (mips_cpu == CPU_R4650)
|
||||
if (mips_arch == CPU_R4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
||||
@ -6113,7 +6113,7 @@ macro2 (ip)
|
||||
break;
|
||||
|
||||
case M_S_DOB:
|
||||
if (mips_cpu == CPU_R4650)
|
||||
if (mips_arch == CPU_R4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
||||
@ -7084,14 +7084,14 @@ mips_ip (str, ip)
|
||||
|
||||
assert (strcmp (insn->name, str) == 0);
|
||||
|
||||
if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu, mips_gp32))
|
||||
if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch, mips_gp32))
|
||||
ok = true;
|
||||
else
|
||||
ok = false;
|
||||
|
||||
if (insn->pinfo != INSN_MACRO)
|
||||
{
|
||||
if (mips_cpu == CPU_R4650 && (insn->pinfo & FP_D) != 0)
|
||||
if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
|
||||
ok = false;
|
||||
}
|
||||
|
||||
@ -7110,7 +7110,7 @@ mips_ip (str, ip)
|
||||
static char buf[100];
|
||||
sprintf (buf,
|
||||
_("opcode not supported on this processor: %s (%s)"),
|
||||
mips_cpu_to_str (mips_cpu),
|
||||
mips_cpu_to_str (mips_arch),
|
||||
mips_isa_to_str (mips_opts.isa));
|
||||
|
||||
insn_error = buf;
|
||||
@ -8941,6 +8941,10 @@ struct option md_longopts[] =
|
||||
{"mips5", no_argument, NULL, OPTION_MIPS5},
|
||||
#define OPTION_MIPS64 (OPTION_MD_BASE + 30)
|
||||
{"mips64", no_argument, NULL, OPTION_MIPS64},
|
||||
#define OPTION_MARCH (OPTION_MD_BASE + 31)
|
||||
{"march", required_argument, NULL, OPTION_MARCH},
|
||||
#define OPTION_MTUNE (OPTION_MD_BASE + 32)
|
||||
{"mtune", required_argument, NULL, OPTION_MTUNE},
|
||||
#ifdef OBJ_ELF
|
||||
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
|
||||
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
|
||||
@ -9042,47 +9046,78 @@ md_parse_option (c, arg)
|
||||
mips_opts.isa = ISA_MIPS64;
|
||||
break;
|
||||
|
||||
case OPTION_MTUNE:
|
||||
case OPTION_MARCH:
|
||||
case OPTION_MCPU:
|
||||
{
|
||||
int cpu = CPU_UNKNOWN;
|
||||
|
||||
/* Identify the processor type. */
|
||||
if (strcasecmp (arg, "default") == 0)
|
||||
mips_cpu = CPU_UNKNOWN;
|
||||
else
|
||||
if (strcasecmp (arg, "default") != 0)
|
||||
{
|
||||
const struct mips_cpu_info *ci;
|
||||
|
||||
ci = mips_cpu_info_from_name (arg);
|
||||
if (ci == NULL || ci->is_isa)
|
||||
as_bad (_("invalid architecture -mcpu=%s"), arg);
|
||||
{
|
||||
switch (c)
|
||||
{
|
||||
case OPTION_MTUNE:
|
||||
as_fatal (_("invalid architecture -mtune=%s"), arg);
|
||||
break;
|
||||
case OPTION_MARCH:
|
||||
as_fatal (_("invalid architecture -march=%s"), arg);
|
||||
break;
|
||||
case OPTION_MCPU:
|
||||
as_fatal (_("invalid architecture -mcpu=%s"), arg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
mips_cpu = ci->cpu;
|
||||
cpu = ci->cpu;
|
||||
}
|
||||
|
||||
switch (c)
|
||||
{
|
||||
case OPTION_MTUNE:
|
||||
mips_tune = cpu;
|
||||
break;
|
||||
case OPTION_MARCH:
|
||||
mips_arch = cpu;
|
||||
break;
|
||||
case OPTION_MCPU:
|
||||
mips_cpu = cpu;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case OPTION_M4650:
|
||||
mips_cpu = CPU_R4650;
|
||||
mips_arch = CPU_R4650;
|
||||
mips_tune = CPU_R4650;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4650:
|
||||
break;
|
||||
|
||||
case OPTION_M4010:
|
||||
mips_cpu = CPU_R4010;
|
||||
mips_arch = CPU_R4010;
|
||||
mips_tune = CPU_R4010;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4010:
|
||||
break;
|
||||
|
||||
case OPTION_M4100:
|
||||
mips_cpu = CPU_VR4100;
|
||||
mips_arch = CPU_VR4100;
|
||||
mips_tune = CPU_VR4100;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4100:
|
||||
break;
|
||||
|
||||
case OPTION_M3900:
|
||||
mips_cpu = CPU_R3900;
|
||||
mips_arch = CPU_R3900;
|
||||
mips_tune = CPU_R3900;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M3900:
|
||||
@ -9288,7 +9323,7 @@ MIPS options:\n\
|
||||
-mips5 generate MIPS ISA V instructions\n\
|
||||
-mips32 generate MIPS32 ISA instructions\n\
|
||||
-mips64 generate MIPS64 ISA instructions\n\
|
||||
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
|
||||
-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
|
||||
|
||||
first = 1;
|
||||
|
||||
@ -9313,7 +9348,7 @@ MIPS options:\n\
|
||||
fputc ('\n', stream);
|
||||
|
||||
fprintf (stream, _("\
|
||||
-mCPU equivalent to -mcpu=CPU.\n\
|
||||
-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
|
||||
-no-mCPU don't generate code specific to CPU.\n\
|
||||
For -mCPU and -no-mCPU, CPU must be one of:\n"));
|
||||
|
||||
|
||||
@ -121,7 +121,7 @@ For each option @samp{-m@var{nnnn}}, generate code for the MIPS
|
||||
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
|
||||
specific to that chip, and to schedule for that chip's hazards.
|
||||
|
||||
@item -mcpu=@var{cpu}
|
||||
@item -march=@var{cpu}
|
||||
Generate code for a particular MIPS cpu. It is exactly equivalent to
|
||||
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
|
||||
understood. Valid @var{cpu} value are:
|
||||
@ -152,6 +152,16 @@ mips32-4k,
|
||||
sb1
|
||||
@end quotation
|
||||
|
||||
@item -mtune=@var{cpu}
|
||||
Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
|
||||
identical to @samp{-march=@var{cpu}}.
|
||||
|
||||
@item -mcpu=@var{cpu}
|
||||
Generate code and schedule for a particular MIPS cpu. This is exactly
|
||||
equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid
|
||||
@var{cpu} values are identical to @samp{-march=@var{cpu}}.
|
||||
Use of this option is discouraged.
|
||||
|
||||
|
||||
@cindex @code{-nocpp} ignored (MIPS)
|
||||
@item -nocpp
|
||||
|
||||
@ -1,3 +1,37 @@
|
||||
2001-06-28 Eric Christopher <echristo@redhat.com>
|
||||
|
||||
* gas/mips/usd.d: Change for march/mtune.
|
||||
* gas/mips/ulh-xgot.d: Ditto.
|
||||
* gas/mips/uld.d: Ditto.
|
||||
* gas/mips/trunc.d: Ditto.
|
||||
* gas/mips/rol.d: Ditto.
|
||||
* gas/mips/nodelay.d: Ditto.
|
||||
* gas/mips/mul.d: Ditto.
|
||||
* gas/mips/mul-ilocks.d: Ditto.
|
||||
* gas/mips/trap20.d: Ditto.
|
||||
* gas/mips/mips4.d: Ditto.
|
||||
* gas/mips/mips16.d: Ditto.
|
||||
* gas/mips/lif-xgot.d: Ditto.
|
||||
* gas/mips/lif-svr4pic.d: Ditto.
|
||||
* gas/mips/ld-xgot.d: Ditto.
|
||||
* gas/mips/ld-svr4pic.d: Ditto.
|
||||
* gas/mips/ld-ilocks-addr32.d: Ditto.
|
||||
* gas/mips/lb-xgot.d: Ditto.
|
||||
* gas/mips/jal-xgot.d: Ditto.
|
||||
* gas/mips/jal-svr4pic.d: Ditto.
|
||||
* gas/mips/delay.d: Ditto.
|
||||
* gas/mips/lb-xgot-ilocks.d: Ditto.
|
||||
* gas/mips/div.d: Ditto.
|
||||
* gas/mips/break20.d: Ditto.
|
||||
* gas/mips/delay.d: Ditto.
|
||||
* gas/mips/elf_e_flags3.d: Ditto.
|
||||
* gas/mips/elf_e_flags4.d: Ditto.
|
||||
* gas/mips/lineno.d: Ditto.
|
||||
* gas/mips/mips16.d: Ditto.
|
||||
* gas/mips/mips4.d: Ditto.
|
||||
* gas/mips/mips4010.d: Ditto.
|
||||
* gas/mips/mips4650.d: Ditto.
|
||||
|
||||
2001-06-21 Nick Clifton <nickc@cambridge.redhat.com>
|
||||
|
||||
* gas/arm/arm.exp: Remove msr-bad.s test.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
#as: -mcpu=r3900
|
||||
#as: -march=r3900
|
||||
#objdump: -dr --prefix-addresses -mmips:3900
|
||||
#name: MIPS 20-bit break
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#name: MIPS delay
|
||||
#as: -mips3 -mcpu=r4000
|
||||
#as: -mips3 -mtune=r4000
|
||||
|
||||
#
|
||||
# Gas should produce nop's after mtc1 and related
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#as: -march=r4000 -mtune=r4000
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#as: -mcpu=r4000
|
||||
#name: MIPS div
|
||||
|
||||
# Test the div macro.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# name: ELF e_flags: -mcpu=4650
|
||||
# name: ELF e_flags: -march=4650 -mtune=4650
|
||||
# source: elf_e_flags.s
|
||||
# as: -mcpu=4650
|
||||
# as: -march=4650 -mtune=4650
|
||||
# objdump: -fd
|
||||
|
||||
.*:.*file format.*mips.*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# name: ELF e_flags: -m4650 -mcpu=4650
|
||||
# name: ELF e_flags: -march=4650 -mtune=4650
|
||||
# source: elf_e_flags.s
|
||||
# as: -m4650 -mcpu=4650
|
||||
# as: -march=4650 -mtune=4650
|
||||
# objdump: -fd
|
||||
|
||||
.*:.*file format.*mips.*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS R3000 jal-svr4pic
|
||||
#as: -mips1 -KPIC -mcpu=r3000
|
||||
#as: -mips1 -KPIC -mtune=r3000
|
||||
|
||||
# Test the jal macro with -KPIC.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS R3000 jal-xgot
|
||||
#as: -mips1 -KPIC -xgot -mcpu=r3000
|
||||
#as: -mips1 -KPIC -xgot -mtune=r3000
|
||||
#source: jal-svr4pic.s
|
||||
|
||||
# Test the jal macro with -KPIC -xgot.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS lb-xgot-ilocks
|
||||
#as: -mips1 -KPIC -xgot -mcpu=r3900
|
||||
#as: -mips1 -KPIC -xgot -mtune=r3900
|
||||
#source: lb-pic.s
|
||||
|
||||
# Test the lb macro with -KPIC -xgot.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS lb-xgot
|
||||
#as: -mips1 -KPIC -xgot -mcpu=r3000
|
||||
#as: -mips1 -KPIC -xgot -mtune=r3000
|
||||
#source: lb-pic.s
|
||||
|
||||
# Test the lb macro with -KPIC -xgot.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#as: -mips3 -mcpu=r4000
|
||||
#as: -mips3 -mtune=r4000 -march=r4000
|
||||
#name: MIPS ld-ilocks
|
||||
#source: ld.s
|
||||
|
||||
@ -629,4 +629,3 @@ Disassembly of section .text:
|
||||
0+05c4 <[^>]*> sd a0,-23131\(at\)
|
||||
[ ]*5c4: [A-Z0-9_]*LO[A-Z0-9_]* .sbss.*
|
||||
0+05c8 <[^>]*> nop
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS ld-svr4pic
|
||||
#as: -mips1 -mcpu=r3000 -KPIC
|
||||
#as: -mips1 -mtune=r3000 -KPIC
|
||||
#source: ld-pic.s
|
||||
|
||||
# Test the ld macro with -KPIC.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS ld-xgot
|
||||
#as: -mips1 -mcpu=r3000 -KPIC -xgot
|
||||
#as: -mips1 -mtune=r3000 -KPIC -xgot
|
||||
#source: ld-pic.s
|
||||
|
||||
# Test the ld macro with -KPIC -xgot.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#as: -mcpu=r4000
|
||||
#as: -march=r4000
|
||||
#name: MIPS ld
|
||||
|
||||
# Test the ld macro.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS lifloat-svr4pic
|
||||
#as: -mips1 -mcpu=r3000 -KPIC -EB --defsym SVR4=1
|
||||
#as: -mips1 -mtune=r3000 -KPIC -EB --defsym SVR4=1
|
||||
#source: lifloat.s
|
||||
|
||||
# Test the li.d and li.s macros with -KPIC.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS lifloat-xgot
|
||||
#as: -mips1 -mcpu=r3000 -KPIC -xgot -EB --defsym XGOT=1
|
||||
#as: -mips1 -mtune=r3000 -KPIC -xgot -EB --defsym XGOT=1
|
||||
#source: lifloat.s
|
||||
|
||||
# Test the li.d and li.s macros with -KPIC -xgot.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -d -l -mmips:4000
|
||||
#name: assembly line numbers
|
||||
#as: -g -mcpu=r4000
|
||||
#as: -g -march=r4000
|
||||
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#objdump: -dr -mmips:4000
|
||||
#as: -mips3 -mcpu=r4000
|
||||
#as: -mips3 -mtune=r4000
|
||||
#name: mips16
|
||||
|
||||
# Test the mips16 instruction set.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:5000
|
||||
#name: MIPS mips4
|
||||
#as: -mips4 -mcpu=r5000
|
||||
#as: -mips4 -mtune=r5000
|
||||
|
||||
# Test the mips4 macros.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4010
|
||||
#name: MIPS 4010
|
||||
#as: -mcpu=4010
|
||||
#as: -march=4010
|
||||
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4100
|
||||
#name: MIPS 4100
|
||||
#as: -mcpu=4100
|
||||
#as: -march=4100
|
||||
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4650
|
||||
#name: MIPS 4650
|
||||
#as: -mcpu=4650
|
||||
#as: -march=4650 -mtune=4650
|
||||
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses
|
||||
#name: MIPS mul-ilocks
|
||||
#as:
|
||||
#as: -march=r4000 -mtune=r4000
|
||||
#source: mul.s
|
||||
|
||||
# Test the mul macro.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#as: -mcpu=r4000
|
||||
#as: -march=r4000 -mtune=r4000
|
||||
#name: MIPS mul
|
||||
|
||||
# Test the mul macro.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:5000
|
||||
#name: MIPS nodelay
|
||||
#as: -mips4 -mcpu=r8000
|
||||
#as: -mips4 -mtune=r8000
|
||||
#source: delay.s
|
||||
|
||||
# For -mips4
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#as: -mcpu=r3000
|
||||
#as: -march=r3000 -mtune=r3000
|
||||
#name: MIPS R3000 rol
|
||||
|
||||
# Test the rol and ror macros.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
#as: -mcpu=r4000
|
||||
#as: -march=r4000
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#name: MIPS 20-bit trap
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS trunc
|
||||
#as: -mips1 -mcpu=r3000
|
||||
#as: -mips1 -mtune=r3000
|
||||
|
||||
# Test the trunc macros.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#name: MIPS uld
|
||||
#as: -mips3 -mcpu=r4000
|
||||
#as: -mips3 -mtune=r4000
|
||||
|
||||
# Test the uld macro.
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:3000
|
||||
#name: MIPS ulh-xgot
|
||||
#as: -mips1 -mcpu=r3000 -KPIC -xgot -EB --defsym XGOT=1
|
||||
#as: -mips1 -mtune=r3000 -KPIC -xgot -EB --defsym XGOT=1
|
||||
#source: ulh-pic.s
|
||||
|
||||
# Test the unaligned load and store macros with -KPIC -xgot.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#objdump: -dr --prefix-addresses -mmips:4000
|
||||
#name: MIPS usd
|
||||
#as: -mips3 -mcpu=r4000
|
||||
#as: -mips3 -mtune=r4000
|
||||
|
||||
# Test the usd macro.
|
||||
|
||||
|
||||
Reference in New Issue
Block a user