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Add support for parallel instructions.

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This commit is contained in:
Nick Clifton
1998-01-15 01:58:34 +00:00
parent df5b318730
commit ebde3f6235
3 changed files with 429 additions and 228 deletions
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6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
Wed Jan 14 17:52:33 1998 Nick Clifton <nickc@cygnus.com>
* config/tc-m32r.c (md_assemble): Add support for parsing parallel
instructions.
* cgen.c: Formatting changes to improve readability.
Wed Jan 14 15:41:41 1998 Jeffrey A Law (law@cygnus.com)
* config/tc-mips.c (macro): Rework division code to avoid unfilled

7
gas/cgen.c
View File

@ -272,7 +272,8 @@ cgen_asm_finish_insn (insn, buf, length)
cgen_insn_t * buf;
unsigned int length;
{
int i, relax_operand;
int i;
int relax_operand;
char * f;
unsigned int byte_len = length / 8;
@ -323,10 +324,13 @@ cgen_asm_finish_insn (insn, buf, length)
/* Ensure variable part and fixed part are in same fragment. */
/* FIXME: Having to do this seems like a hack. */
frag_grow (max_len);
/* Allocate space for the fixed part. */
f = frag_more (byte_len);
/* Create a relaxable fragment for this instruction. */
old_frag = frag_now;
frag_var (rs_machine_dependent,
max_len - byte_len /* max chars */,
0 /* variable part already allocated */,
@ -336,6 +340,7 @@ cgen_asm_finish_insn (insn, buf, length)
fixups[relax_operand].exp.X_add_symbol,
fixups[relax_operand].exp.X_add_number,
f);
/* Record the operand number with the fragment so md_convert_frag
can use cgen_md_record_fixup to record the appropriate reloc. */
old_frag->fr_cgen.insn = insn;

228
gas/config/tc-m32r.c
View File

@ -24,6 +24,9 @@
#include "subsegs.h"
#include "cgen-opc.h"
#include "../../opcodes/m32r-asm.c"
#include "../../opcodes/m32r-asm.in"
/* Non-null if last insn was a 16 bit insn on a 32 bit boundary
(i.e. was the first of two 16 bit insns). */
static const CGEN_INSN * prev_insn = NULL;
@ -45,7 +48,6 @@ static char *m32r_cpu_desc;
/* start-sanitize-m32rx */
/* Non-zero if -m32rx has been specified, in which case support for the
extended M32RX instruction set should be enabled. */
/* Indicates the target BFD machine number. */
static int enable_m32rx = 0;
/* end-sanitize-m32rx */
@ -73,12 +75,10 @@ const char FLT_CHARS[] = "dD";
struct m32r_hi_fixup
{
/* Next HI fixup. */
struct m32r_hi_fixup *next;
/* This fixup. */
fixS *fixp;
/* The section this fixup is in. */
segT seg;
struct m32r_hi_fixup * next; /* Next HI fixup. */
fixS * fixp; /* This fixup. */
segT seg; /* The section this fixup is in. */
};
/* The list of unmatched HI relocs. */
@ -95,7 +95,8 @@ allow_m32rx (int on)
enable_m32rx = on;
if (stdoutput != NULL)
bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
bfd_set_arch_mach (stdoutput, TARGET_ARCH,
enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
}
/* end-sanitize-m32rx */
@ -224,7 +225,8 @@ m32r_do_align (n, fill, len, max)
nops. */
if (n > 2)
{
static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
static const unsigned char multi_nop_pattern[] =
{ 0x70, 0x00, 0xf0, 0x00 };
frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
max ? max - 2 : 0);
}
@ -276,10 +278,14 @@ m32r_fill_insn (done)
{
seg = now_seg;
subseg = now_subseg;
subseg_set (prev_seg, prev_subseg);
fill_insn (0);
subseg_set (seg, subseg);
}
return 1;
}
@ -294,9 +300,11 @@ md_begin ()
/* This is a callback from cgen to gas to parse operands. */
cgen_parse_operand_fn = cgen_parse_operand;
/* Set the machine number and endian. */
CGEN_SYM (init_asm) (0 /* mach number */,
target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
target_big_endian ?
CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
#if 0 /* not supported yet */
/* If a runtime cpu description file was provided, parse it. */
@ -311,15 +319,17 @@ md_begin ()
#endif
/* Save the current subseg so we can restore it [it's the default one and
we don't want the initial section to be .sbss. */
we don't want the initial section to be .sbss]. */
seg = now_seg;
subseg = now_subseg;
/* The sbss section is for local .scomm symbols. */
sbss_section = subseg_new (".sbss", 0);
/* This is copied from perform_an_assembly_pass. */
applicable = bfd_applicable_section_flags (stdoutput);
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
#if 0 /* What does this do? [see perform_an_assembly_pass] */
seg_info (bss_section)->bss = 1;
#endif
@ -342,22 +352,99 @@ md_begin ()
/* end-sanitize-m32rx */
}
/* Returns non zero if the given instruction writes to a destination register. */
static int
writes_to_dest_reg (insn)
const CGEN_INSN * insn;
{
unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
unsigned char c;
/* Scan the syntax string looking for a destination register. */
while ((c = (* syntax ++)) != 0)
if (c == 128 + M32R_OPERAND_DR)
break;
return c;
}
/* Returns an integer representing the destination register of
the given insn, or -1 if the insn has no destination. */
static int
get_dest_reg (insn)
const CGEN_INSN * insn;
{
/* XXX to be done. */
return -1;
}
void
md_assemble (str)
char * str;
{
#ifdef CGEN_INT_INSN
cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
cgen_insn_t prev_buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
#else
char buffer [CGEN_MAX_INSN_SIZE];
char prev_buffer [CGEN_MAX_INSN_SIZE];
#endif
CGEN_FIELDS fields;
CGEN_FIELDS prev_fields;
const CGEN_INSN * insn;
char * errmsg;
char * str2 = NULL;
int is_parallel = false;
/* Initialize GAS's cgen interface for a new instruction. */
cgen_asm_init_parse ();
/* Look for a parallel instruction seperator. */
if ((str2 = strstr (str, "||")) != NULL)
{
char * str3;
* str2 = 0; /* Seperate the two instructions. */
/* If there was a previous 16 bit insn, then fill the following 16 bit slot,
so that the parallel instruction will start on a 32 bit boundary. */
if (prev_insn)
fill_insn (0);
/* Assemble the first instruction. */
prev_insn = CGEN_SYM (assemble_insn) (str, & prev_fields, prev_buffer, & errmsg);
if (! prev_insn)
{
as_bad (errmsg);
return;
}
/* Check to see if this is an allowable parallel insn. */
if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
as_bad ("instruction '%s' cannot be executed in parallel.", str);
return;
}
/* start-sanitize-m32rx */
if (! enable_m32rx &&
CGEN_INSN_ATTR (prev_insn, CGEN_INSN_MACH) == MACH_M32RX)
{
as_bad ("instruction '%s' is for the M32RX only", str);
return;
}
/* end-sanitize-m32rx */
/* fixups = fixups->next; */
*str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
str3 = str; /* Save the original string pointer. */
str = str2 + 2; /* Advanced past the parsed string. */
str2 = str3; /* Remember the entire string in case it is needed for error messages. */
is_parallel = true;
}
insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
if (!insn)
{
@ -365,13 +452,106 @@ md_assemble (str)
return;
}
if (CGEN_INSN_BITSIZE (insn) == 32)
/* start-sanitize-m32rx */
if (! enable_m32rx
&& CGEN_INSN_ATTR (insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
as_bad ("instruction '%s' is for the M32RX only", str);
return;
}
/* end-sanitize-m32rx */
if (is_parallel)
{
/* start-sanitize-m32rx */
if (! enable_m32rx)
{
if (strcmp (prev_insn->name, "nop") != 0
&& strcmp (insn->name, "nop") != 0)
{
as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
return;
}
}
/* end-sanitize-m32rx */
/* Check to see if this is an allowable parallel insn. */
if (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
as_bad ("instruction '%s', cannot be executed in parallel.", str);
return;
}
/* Check to see that the two instructions can be placed in parallel. */
if ((CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE))
&& (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) != PIPE_OS))
{
as_bad ("'%s': both instructions use the same execution pipeline", str2);
return;
}
#if 0
/* Check that the instructions do not write to the same destination register. */
if (writes_to_dest_reg (insn)
&& writes_to_dest_reg (prev_insn) /* This test is actually redundant. */
&& get_dest_reg (insn) == get_dest_reg (prev_insn))
{
as_bad ("'%s': both instructions write to the same destination register", str2);
return;
}
#endif
/* Force the top bit of the second insn to be set. */
#if 0 /*def CGEN_INT_INSN*/
#define MAKE_PARALLEL(insn) ((insn) |= 0x8000)
switch (CGEN_FIELDS_BITSIZE (& fields))
{
bfd_vma value;
case 16:
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
{
value = bfd_getb16 ((bfd_vma) * buffer);
MAKE_PARALLEL (value);
bfd_putb16 (value, buffer);
}
else
{
value = bfd_getl16 ((bfd_vma) * buffer);
MAKE_PARALLEL (value);
bfd_putl16 (value, buffer);
}
break;
default:
abort ();
}
#else
#define MAKE_PARALLEL(insn) ((insn) |= 0x80)
MAKE_PARALLEL (buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1]);
#endif
/* Generate the parallel instructions */
cgen_asm_finish_insn (prev_insn, prev_buffer, CGEN_FIELDS_BITSIZE (& prev_fields));
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
/* If prev_ins is relaxable (and insn is not), then swap them, so that the test
after the end of this if-then-else section will work. */
if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_RELAXABLE))
insn = prev_insn;
/* Clear the prev_insn variable, since it only used if the insn was the first
16 bit insn in a 32 bit word. */
prev_insn = NULL;
}
else if (CGEN_INSN_BITSIZE (insn) == 32)
{
/* 32 bit insns must live on 32 bit boundaries. */
if (prev_insn || seen_relaxable_p)
{
/* FIXME: If calling fill_insn too many times turns us into a memory
pig, can we call assemble_nop instead of !seen_relaxable_p? */
if (prev_insn || seen_relaxable_p)
fill_insn (0);
}
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
}
else
@ -382,6 +562,7 @@ md_assemble (str)
prev_insn = NULL;
else
prev_insn = insn;
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
/* If the insn needs the following one to be on a 32 bit boundary
@ -717,8 +898,12 @@ md_convert_frag (abfd, sec, fragP)
segT sec;
fragS *fragP;
{
char *opcode, *displacement;
int target_address, opcode_address, extension, addend;
char * opcode;
char * displacement;
int target_address;
int opcode_address;
int extension;
int addend;
opcode = fragP->fr_opcode;
@ -888,6 +1073,7 @@ m32r_record_hi16 (reloc_type, fixP, seg)
hi_fixup->fixp = fixP;
hi_fixup->seg = now_seg;
hi_fixup->next = m32r_hi_fixup_list;
m32r_hi_fixup_list = hi_fixup;
}
@ -928,7 +1114,8 @@ m32r_frob_file ()
seginfo = seg_info (l->seg);
for (pass = 0; pass < 2; pass++)
{
fixS *f, *prev;
fixS * f;
fixS * prev;
prev = NULL;
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
@ -1019,7 +1206,8 @@ md_atof (type, litP, sizeP)
char *litP;
int *sizeP;
{
int i,prec;
int i;
int prec;
LITTLENUM_TYPE words [MAX_LITTLENUMS];
LITTLENUM_TYPE * wordP;
char * t;
@ -1057,7 +1245,8 @@ md_atof (type, litP, sizeP)
{
for (i = 0; i < prec; i++)
{
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
@ -1065,7 +1254,8 @@ md_atof (type, litP, sizeP)
{
for (i = prec - 1; i >= 0; i--)
{
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}