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Add support for parallel instructions.
This commit is contained in:
@ -1,3 +1,9 @@
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Wed Jan 14 17:52:33 1998 Nick Clifton <nickc@cygnus.com>
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* config/tc-m32r.c (md_assemble): Add support for parsing parallel
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instructions.
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* cgen.c: Formatting changes to improve readability.
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Wed Jan 14 15:41:41 1998 Jeffrey A Law (law@cygnus.com)
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Wed Jan 14 15:41:41 1998 Jeffrey A Law (law@cygnus.com)
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* config/tc-mips.c (macro): Rework division code to avoid unfilled
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* config/tc-mips.c (macro): Rework division code to avoid unfilled
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@ -272,7 +272,8 @@ cgen_asm_finish_insn (insn, buf, length)
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cgen_insn_t * buf;
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cgen_insn_t * buf;
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unsigned int length;
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unsigned int length;
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{
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{
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int i, relax_operand;
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int i;
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int relax_operand;
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char * f;
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char * f;
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unsigned int byte_len = length / 8;
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unsigned int byte_len = length / 8;
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@ -323,10 +324,13 @@ cgen_asm_finish_insn (insn, buf, length)
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/* Ensure variable part and fixed part are in same fragment. */
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/* Ensure variable part and fixed part are in same fragment. */
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/* FIXME: Having to do this seems like a hack. */
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/* FIXME: Having to do this seems like a hack. */
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frag_grow (max_len);
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frag_grow (max_len);
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/* Allocate space for the fixed part. */
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/* Allocate space for the fixed part. */
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f = frag_more (byte_len);
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f = frag_more (byte_len);
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/* Create a relaxable fragment for this instruction. */
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/* Create a relaxable fragment for this instruction. */
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old_frag = frag_now;
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old_frag = frag_now;
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frag_var (rs_machine_dependent,
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frag_var (rs_machine_dependent,
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max_len - byte_len /* max chars */,
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max_len - byte_len /* max chars */,
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0 /* variable part already allocated */,
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0 /* variable part already allocated */,
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@ -336,6 +340,7 @@ cgen_asm_finish_insn (insn, buf, length)
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fixups[relax_operand].exp.X_add_symbol,
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fixups[relax_operand].exp.X_add_symbol,
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fixups[relax_operand].exp.X_add_number,
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fixups[relax_operand].exp.X_add_number,
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f);
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f);
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/* Record the operand number with the fragment so md_convert_frag
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/* Record the operand number with the fragment so md_convert_frag
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can use cgen_md_record_fixup to record the appropriate reloc. */
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can use cgen_md_record_fixup to record the appropriate reloc. */
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old_frag->fr_cgen.insn = insn;
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old_frag->fr_cgen.insn = insn;
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@ -24,6 +24,9 @@
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#include "subsegs.h"
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#include "subsegs.h"
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#include "cgen-opc.h"
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#include "cgen-opc.h"
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#include "../../opcodes/m32r-asm.c"
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#include "../../opcodes/m32r-asm.in"
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/* Non-null if last insn was a 16 bit insn on a 32 bit boundary
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/* Non-null if last insn was a 16 bit insn on a 32 bit boundary
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(i.e. was the first of two 16 bit insns). */
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(i.e. was the first of two 16 bit insns). */
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static const CGEN_INSN * prev_insn = NULL;
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static const CGEN_INSN * prev_insn = NULL;
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@ -45,7 +48,6 @@ static char *m32r_cpu_desc;
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/* start-sanitize-m32rx */
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/* start-sanitize-m32rx */
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/* Non-zero if -m32rx has been specified, in which case support for the
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/* Non-zero if -m32rx has been specified, in which case support for the
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extended M32RX instruction set should be enabled. */
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extended M32RX instruction set should be enabled. */
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/* Indicates the target BFD machine number. */
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static int enable_m32rx = 0;
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static int enable_m32rx = 0;
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/* end-sanitize-m32rx */
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/* end-sanitize-m32rx */
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@ -73,12 +75,10 @@ const char FLT_CHARS[] = "dD";
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struct m32r_hi_fixup
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struct m32r_hi_fixup
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{
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{
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/* Next HI fixup. */
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struct m32r_hi_fixup * next; /* Next HI fixup. */
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struct m32r_hi_fixup *next;
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fixS * fixp; /* This fixup. */
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/* This fixup. */
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segT seg; /* The section this fixup is in. */
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fixS *fixp;
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/* The section this fixup is in. */
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segT seg;
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};
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};
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/* The list of unmatched HI relocs. */
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/* The list of unmatched HI relocs. */
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@ -95,7 +95,8 @@ allow_m32rx (int on)
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enable_m32rx = on;
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enable_m32rx = on;
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if (stdoutput != NULL)
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if (stdoutput != NULL)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
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bfd_set_arch_mach (stdoutput, TARGET_ARCH,
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enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
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}
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-m32rx */
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@ -224,7 +225,8 @@ m32r_do_align (n, fill, len, max)
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nops. */
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nops. */
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if (n > 2)
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if (n > 2)
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{
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{
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static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
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static const unsigned char multi_nop_pattern[] =
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{ 0x70, 0x00, 0xf0, 0x00 };
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frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
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frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
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max ? max - 2 : 0);
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max ? max - 2 : 0);
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}
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}
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@ -276,10 +278,14 @@ m32r_fill_insn (done)
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{
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{
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seg = now_seg;
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seg = now_seg;
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subseg = now_subseg;
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subseg = now_subseg;
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subseg_set (prev_seg, prev_subseg);
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subseg_set (prev_seg, prev_subseg);
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fill_insn (0);
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fill_insn (0);
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subseg_set (seg, subseg);
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subseg_set (seg, subseg);
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}
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}
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return 1;
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return 1;
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}
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}
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@ -294,9 +300,11 @@ md_begin ()
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/* This is a callback from cgen to gas to parse operands. */
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/* This is a callback from cgen to gas to parse operands. */
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cgen_parse_operand_fn = cgen_parse_operand;
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cgen_parse_operand_fn = cgen_parse_operand;
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/* Set the machine number and endian. */
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/* Set the machine number and endian. */
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CGEN_SYM (init_asm) (0 /* mach number */,
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CGEN_SYM (init_asm) (0 /* mach number */,
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target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
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target_big_endian ?
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CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
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#if 0 /* not supported yet */
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#if 0 /* not supported yet */
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/* If a runtime cpu description file was provided, parse it. */
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/* If a runtime cpu description file was provided, parse it. */
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@ -311,15 +319,17 @@ md_begin ()
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#endif
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#endif
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/* Save the current subseg so we can restore it [it's the default one and
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/* Save the current subseg so we can restore it [it's the default one and
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we don't want the initial section to be .sbss. */
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we don't want the initial section to be .sbss]. */
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seg = now_seg;
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seg = now_seg;
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subseg = now_subseg;
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subseg = now_subseg;
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/* The sbss section is for local .scomm symbols. */
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/* The sbss section is for local .scomm symbols. */
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sbss_section = subseg_new (".sbss", 0);
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sbss_section = subseg_new (".sbss", 0);
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/* This is copied from perform_an_assembly_pass. */
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/* This is copied from perform_an_assembly_pass. */
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applicable = bfd_applicable_section_flags (stdoutput);
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applicable = bfd_applicable_section_flags (stdoutput);
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bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
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bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
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#if 0 /* What does this do? [see perform_an_assembly_pass] */
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#if 0 /* What does this do? [see perform_an_assembly_pass] */
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seg_info (bss_section)->bss = 1;
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seg_info (bss_section)->bss = 1;
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#endif
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#endif
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@ -342,22 +352,99 @@ md_begin ()
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/* end-sanitize-m32rx */
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/* end-sanitize-m32rx */
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}
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}
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/* Returns non zero if the given instruction writes to a destination register. */
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static int
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writes_to_dest_reg (insn)
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const CGEN_INSN * insn;
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{
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unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
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unsigned char c;
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/* Scan the syntax string looking for a destination register. */
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while ((c = (* syntax ++)) != 0)
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if (c == 128 + M32R_OPERAND_DR)
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break;
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return c;
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}
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/* Returns an integer representing the destination register of
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the given insn, or -1 if the insn has no destination. */
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static int
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get_dest_reg (insn)
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const CGEN_INSN * insn;
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{
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/* XXX to be done. */
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return -1;
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}
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void
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void
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md_assemble (str)
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md_assemble (str)
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char * str;
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char * str;
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{
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{
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#ifdef CGEN_INT_INSN
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#ifdef CGEN_INT_INSN
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cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
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cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
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cgen_insn_t prev_buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
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#else
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#else
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char buffer [CGEN_MAX_INSN_SIZE];
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char buffer [CGEN_MAX_INSN_SIZE];
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char prev_buffer [CGEN_MAX_INSN_SIZE];
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#endif
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#endif
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CGEN_FIELDS fields;
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CGEN_FIELDS fields;
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CGEN_FIELDS prev_fields;
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const CGEN_INSN * insn;
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const CGEN_INSN * insn;
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char * errmsg;
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char * errmsg;
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char * str2 = NULL;
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int is_parallel = false;
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/* Initialize GAS's cgen interface for a new instruction. */
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/* Initialize GAS's cgen interface for a new instruction. */
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cgen_asm_init_parse ();
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cgen_asm_init_parse ();
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/* Look for a parallel instruction seperator. */
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if ((str2 = strstr (str, "||")) != NULL)
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{
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char * str3;
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* str2 = 0; /* Seperate the two instructions. */
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/* If there was a previous 16 bit insn, then fill the following 16 bit slot,
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so that the parallel instruction will start on a 32 bit boundary. */
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|
if (prev_insn)
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fill_insn (0);
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|
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/* Assemble the first instruction. */
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prev_insn = CGEN_SYM (assemble_insn) (str, & prev_fields, prev_buffer, & errmsg);
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|
if (! prev_insn)
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{
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as_bad (errmsg);
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|
return;
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|
}
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|
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/* Check to see if this is an allowable parallel insn. */
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if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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as_bad ("instruction '%s' cannot be executed in parallel.", str);
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return;
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|
}
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|
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|
/* start-sanitize-m32rx */
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|
if (! enable_m32rx &&
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|
CGEN_INSN_ATTR (prev_insn, CGEN_INSN_MACH) == MACH_M32RX)
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{
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|
as_bad ("instruction '%s' is for the M32RX only", str);
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|
return;
|
||||||
|
}
|
||||||
|
/* end-sanitize-m32rx */
|
||||||
|
|
||||||
|
/* fixups = fixups->next; */
|
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|
|
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*str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
|
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|
str3 = str; /* Save the original string pointer. */
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|
str = str2 + 2; /* Advanced past the parsed string. */
|
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|
str2 = str3; /* Remember the entire string in case it is needed for error messages. */
|
||||||
|
|
||||||
|
is_parallel = true;
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|
}
|
||||||
|
|
||||||
insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
|
insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
|
||||||
if (!insn)
|
if (!insn)
|
||||||
{
|
{
|
||||||
@ -365,13 +452,106 @@ md_assemble (str)
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (CGEN_INSN_BITSIZE (insn) == 32)
|
/* start-sanitize-m32rx */
|
||||||
|
if (! enable_m32rx
|
||||||
|
&& CGEN_INSN_ATTR (insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
||||||
|
{
|
||||||
|
as_bad ("instruction '%s' is for the M32RX only", str);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
/* end-sanitize-m32rx */
|
||||||
|
|
||||||
|
if (is_parallel)
|
||||||
|
{
|
||||||
|
/* start-sanitize-m32rx */
|
||||||
|
if (! enable_m32rx)
|
||||||
|
{
|
||||||
|
if (strcmp (prev_insn->name, "nop") != 0
|
||||||
|
&& strcmp (insn->name, "nop") != 0)
|
||||||
|
{
|
||||||
|
as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* end-sanitize-m32rx */
|
||||||
|
|
||||||
|
/* Check to see if this is an allowable parallel insn. */
|
||||||
|
if (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
||||||
|
{
|
||||||
|
as_bad ("instruction '%s', cannot be executed in parallel.", str);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check to see that the two instructions can be placed in parallel. */
|
||||||
|
if ((CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE))
|
||||||
|
&& (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) != PIPE_OS))
|
||||||
|
{
|
||||||
|
as_bad ("'%s': both instructions use the same execution pipeline", str2);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#if 0
|
||||||
|
/* Check that the instructions do not write to the same destination register. */
|
||||||
|
if (writes_to_dest_reg (insn)
|
||||||
|
&& writes_to_dest_reg (prev_insn) /* This test is actually redundant. */
|
||||||
|
&& get_dest_reg (insn) == get_dest_reg (prev_insn))
|
||||||
|
{
|
||||||
|
as_bad ("'%s': both instructions write to the same destination register", str2);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Force the top bit of the second insn to be set. */
|
||||||
|
#if 0 /*def CGEN_INT_INSN*/
|
||||||
|
#define MAKE_PARALLEL(insn) ((insn) |= 0x8000)
|
||||||
|
switch (CGEN_FIELDS_BITSIZE (& fields))
|
||||||
|
{
|
||||||
|
bfd_vma value;
|
||||||
|
|
||||||
|
case 16:
|
||||||
|
if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
|
||||||
|
{
|
||||||
|
value = bfd_getb16 ((bfd_vma) * buffer);
|
||||||
|
MAKE_PARALLEL (value);
|
||||||
|
bfd_putb16 (value, buffer);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
value = bfd_getl16 ((bfd_vma) * buffer);
|
||||||
|
MAKE_PARALLEL (value);
|
||||||
|
bfd_putl16 (value, buffer);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
abort ();
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define MAKE_PARALLEL(insn) ((insn) |= 0x80)
|
||||||
|
MAKE_PARALLEL (buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1]);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Generate the parallel instructions */
|
||||||
|
cgen_asm_finish_insn (prev_insn, prev_buffer, CGEN_FIELDS_BITSIZE (& prev_fields));
|
||||||
|
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
|
||||||
|
|
||||||
|
/* If prev_ins is relaxable (and insn is not), then swap them, so that the test
|
||||||
|
after the end of this if-then-else section will work. */
|
||||||
|
if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_RELAXABLE))
|
||||||
|
insn = prev_insn;
|
||||||
|
|
||||||
|
/* Clear the prev_insn variable, since it only used if the insn was the first
|
||||||
|
16 bit insn in a 32 bit word. */
|
||||||
|
prev_insn = NULL;
|
||||||
|
}
|
||||||
|
else if (CGEN_INSN_BITSIZE (insn) == 32)
|
||||||
{
|
{
|
||||||
/* 32 bit insns must live on 32 bit boundaries. */
|
/* 32 bit insns must live on 32 bit boundaries. */
|
||||||
|
if (prev_insn || seen_relaxable_p)
|
||||||
|
{
|
||||||
/* FIXME: If calling fill_insn too many times turns us into a memory
|
/* FIXME: If calling fill_insn too many times turns us into a memory
|
||||||
pig, can we call assemble_nop instead of !seen_relaxable_p? */
|
pig, can we call assemble_nop instead of !seen_relaxable_p? */
|
||||||
if (prev_insn || seen_relaxable_p)
|
|
||||||
fill_insn (0);
|
fill_insn (0);
|
||||||
|
}
|
||||||
|
|
||||||
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
|
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
@ -382,6 +562,7 @@ md_assemble (str)
|
|||||||
prev_insn = NULL;
|
prev_insn = NULL;
|
||||||
else
|
else
|
||||||
prev_insn = insn;
|
prev_insn = insn;
|
||||||
|
|
||||||
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
|
cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
|
||||||
|
|
||||||
/* If the insn needs the following one to be on a 32 bit boundary
|
/* If the insn needs the following one to be on a 32 bit boundary
|
||||||
@ -717,8 +898,12 @@ md_convert_frag (abfd, sec, fragP)
|
|||||||
segT sec;
|
segT sec;
|
||||||
fragS *fragP;
|
fragS *fragP;
|
||||||
{
|
{
|
||||||
char *opcode, *displacement;
|
char * opcode;
|
||||||
int target_address, opcode_address, extension, addend;
|
char * displacement;
|
||||||
|
int target_address;
|
||||||
|
int opcode_address;
|
||||||
|
int extension;
|
||||||
|
int addend;
|
||||||
|
|
||||||
opcode = fragP->fr_opcode;
|
opcode = fragP->fr_opcode;
|
||||||
|
|
||||||
@ -888,6 +1073,7 @@ m32r_record_hi16 (reloc_type, fixP, seg)
|
|||||||
hi_fixup->fixp = fixP;
|
hi_fixup->fixp = fixP;
|
||||||
hi_fixup->seg = now_seg;
|
hi_fixup->seg = now_seg;
|
||||||
hi_fixup->next = m32r_hi_fixup_list;
|
hi_fixup->next = m32r_hi_fixup_list;
|
||||||
|
|
||||||
m32r_hi_fixup_list = hi_fixup;
|
m32r_hi_fixup_list = hi_fixup;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -928,7 +1114,8 @@ m32r_frob_file ()
|
|||||||
seginfo = seg_info (l->seg);
|
seginfo = seg_info (l->seg);
|
||||||
for (pass = 0; pass < 2; pass++)
|
for (pass = 0; pass < 2; pass++)
|
||||||
{
|
{
|
||||||
fixS *f, *prev;
|
fixS * f;
|
||||||
|
fixS * prev;
|
||||||
|
|
||||||
prev = NULL;
|
prev = NULL;
|
||||||
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
||||||
@ -1019,7 +1206,8 @@ md_atof (type, litP, sizeP)
|
|||||||
char *litP;
|
char *litP;
|
||||||
int *sizeP;
|
int *sizeP;
|
||||||
{
|
{
|
||||||
int i,prec;
|
int i;
|
||||||
|
int prec;
|
||||||
LITTLENUM_TYPE words [MAX_LITTLENUMS];
|
LITTLENUM_TYPE words [MAX_LITTLENUMS];
|
||||||
LITTLENUM_TYPE * wordP;
|
LITTLENUM_TYPE * wordP;
|
||||||
char * t;
|
char * t;
|
||||||
@ -1057,7 +1245,8 @@ md_atof (type, litP, sizeP)
|
|||||||
{
|
{
|
||||||
for (i = 0; i < prec; i++)
|
for (i = 0; i < prec; i++)
|
||||||
{
|
{
|
||||||
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
md_number_to_chars (litP, (valueT) words[i],
|
||||||
|
sizeof (LITTLENUM_TYPE));
|
||||||
litP += sizeof (LITTLENUM_TYPE);
|
litP += sizeof (LITTLENUM_TYPE);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1065,7 +1254,8 @@ md_atof (type, litP, sizeP)
|
|||||||
{
|
{
|
||||||
for (i = prec - 1; i >= 0; i--)
|
for (i = prec - 1; i >= 0; i--)
|
||||||
{
|
{
|
||||||
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
|
md_number_to_chars (litP, (valueT) words[i],
|
||||||
|
sizeof (LITTLENUM_TYPE));
|
||||||
litP += sizeof (LITTLENUM_TYPE);
|
litP += sizeof (LITTLENUM_TYPE);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
Reference in New Issue
Block a user