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RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:

committed by
Philipp Tomsich

parent
618ba27878
commit
eb668e5003
@ -1162,6 +1162,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
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{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
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{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
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{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
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{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@ -2309,6 +2310,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zmmul");
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return riscv_subset_supports (rps, "zmmul");
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case INSN_CLASS_A:
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case INSN_CLASS_A:
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return riscv_subset_supports (rps, "a");
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return riscv_subset_supports (rps, "a");
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case INSN_CLASS_ZAWRS:
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return riscv_subset_supports (rps, "zawrs");
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case INSN_CLASS_F:
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case INSN_CLASS_F:
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return riscv_subset_supports (rps, "f");
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return riscv_subset_supports (rps, "f");
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case INSN_CLASS_D:
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case INSN_CLASS_D:
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@ -2446,6 +2449,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return _ ("m' or `zmmul");
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return _ ("m' or `zmmul");
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case INSN_CLASS_A:
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case INSN_CLASS_A:
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return "a";
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return "a";
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case INSN_CLASS_ZAWRS:
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return "zawrs";
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case INSN_CLASS_F:
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case INSN_CLASS_F:
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return "f";
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return "f";
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case INSN_CLASS_D:
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case INSN_CLASS_D:
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11
gas/testsuite/gas/riscv/zawrs-32.d
Normal file
11
gas/testsuite/gas/riscv/zawrs-32.d
Normal file
@ -0,0 +1,11 @@
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#as: -march=rv32i_zawrs
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#source: zawrs.s
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+00d00073[ ]+wrs.nto
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[ ]+[0-9a-f]+:[ ]+01d00073[ ]+wrs.sto
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11
gas/testsuite/gas/riscv/zawrs.d
Normal file
11
gas/testsuite/gas/riscv/zawrs.d
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@ -0,0 +1,11 @@
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#as: -march=rv64i_zawrs
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#source: zawrs.s
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+00d00073[ ]+wrs.nto
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[ ]+[0-9a-f]+:[ ]+01d00073[ ]+wrs.sto
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3
gas/testsuite/gas/riscv/zawrs.s
Normal file
3
gas/testsuite/gas/riscv/zawrs.s
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@ -0,0 +1,3 @@
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target:
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wrs.nto
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wrs.sto
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@ -2113,6 +2113,11 @@
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#define MASK_CBO_INVAL 0xfff07fff
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#define MASK_CBO_INVAL 0xfff07fff
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#define MATCH_CBO_ZERO 0x40200f
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#define MATCH_CBO_ZERO 0x40200f
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#define MASK_CBO_ZERO 0xfff07fff
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#define MASK_CBO_ZERO 0xfff07fff
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/* Zawrs intructions. */
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#define MATCH_WRS_NTO 0x00d00073
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#define MASK_WRS_NTO 0xffffffff
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#define MATCH_WRS_STO 0x01d00073
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#define MASK_WRS_STO 0xffffffff
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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#define MATCH_TH_ADDSL 0x0000100b
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#define MATCH_TH_ADDSL 0x0000100b
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#define MASK_TH_ADDSL 0xf800707f
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#define MASK_TH_ADDSL 0xf800707f
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@ -3066,6 +3071,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
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DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
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DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
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DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
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DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
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DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
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DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
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/* Zawrs instructions. */
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DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
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DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
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DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
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/* Vendor-specific (T-Head) XTheadBb instructions. */
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/* Vendor-specific (T-Head) XTheadBb instructions. */
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@ -385,6 +385,7 @@ enum riscv_insn_class
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INSN_CLASS_ZIFENCEI,
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INSN_CLASS_ZIFENCEI,
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INSN_CLASS_ZIHINTPAUSE,
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INSN_CLASS_ZIHINTPAUSE,
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INSN_CLASS_ZMMUL,
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INSN_CLASS_ZMMUL,
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INSN_CLASS_ZAWRS,
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INSN_CLASS_F_OR_ZFINX,
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INSN_CLASS_F_OR_ZFINX,
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INSN_CLASS_D_OR_ZDINX,
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INSN_CLASS_D_OR_ZDINX,
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INSN_CLASS_Q_OR_ZQINX,
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INSN_CLASS_Q_OR_ZQINX,
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@ -950,6 +950,10 @@ const struct riscv_opcode riscv_opcodes[] =
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{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
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{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
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{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
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{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
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/* Zawrs instructions. */
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{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
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{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
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/* Zbb or zbkb instructions. */
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/* Zbb or zbkb instructions. */
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{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
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{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
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{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
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{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
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