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RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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committed by
Philipp Tomsich

parent
618ba27878
commit
eb668e5003
@ -2113,6 +2113,11 @@
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#define MASK_CBO_INVAL 0xfff07fff
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#define MATCH_CBO_ZERO 0x40200f
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#define MASK_CBO_ZERO 0xfff07fff
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/* Zawrs intructions. */
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#define MATCH_WRS_NTO 0x00d00073
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#define MASK_WRS_NTO 0xffffffff
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#define MATCH_WRS_STO 0x01d00073
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#define MASK_WRS_STO 0xffffffff
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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#define MATCH_TH_ADDSL 0x0000100b
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#define MASK_TH_ADDSL 0xf800707f
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@ -3066,6 +3071,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
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DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
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DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
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DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
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/* Zawrs instructions. */
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DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
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DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
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/* Vendor-specific (T-Head) XTheadBb instructions. */
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@ -385,6 +385,7 @@ enum riscv_insn_class
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INSN_CLASS_ZIFENCEI,
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INSN_CLASS_ZIHINTPAUSE,
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INSN_CLASS_ZMMUL,
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INSN_CLASS_ZAWRS,
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INSN_CLASS_F_OR_ZFINX,
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INSN_CLASS_D_OR_ZDINX,
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INSN_CLASS_Q_OR_ZQINX,
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