espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-18 08:38:10 +08:00
Code Issues Packages Projects Releases Wiki Activity

Fri Sep 6 17:56:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>

Browse Source 
* simops.c (OP_2600, OP_2601): Changed min and max comparisons
	to use signed register values.
This commit is contained in:
Martin Hunt
1996-09-07 00:58:25 +00:00
parent 5e6c6406e6
commit ea2155e858
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
sim/d10v/ChangeLog
View File

@ -1,3 +1,8 @@
Fri Sep 6 17:56:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* simops.c (OP_2600, OP_2601): Changed min and max comparisons
to use signed register values.
Wed Sep 4 11:35:17 1996 Michael Meissner <meissner@tiktok.cygnus.com> Wed Sep 4 11:35:17 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v_sim.h (DEBUG_*): Add bit flags for controlling debug * d10v_sim.h (DEBUG_*): Add bit flags for controlling debug

4
sim/d10v/simops.c
View File

@ -1223,7 +1223,7 @@ OP_2600 ()
{ {
trace_input ("max", OP_REG, OP_REG, OP_VOID); trace_input ("max", OP_REG, OP_REG, OP_VOID);
State.F1 = State.F0; State.F1 = State.F0;
if (State.regs[OP[1]] > State.regs[OP[0]]) if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
{ {
State.regs[OP[0]] = State.regs[OP[1]]; State.regs[OP[0]] = State.regs[OP[1]];
State.F0 = 1; State.F0 = 1;
@ -1275,7 +1275,7 @@ OP_2601 ()
{ {
trace_input ("min", OP_REG, OP_REG, OP_VOID); trace_input ("min", OP_REG, OP_REG, OP_VOID);
State.F1 = State.F0; State.F1 = State.F0;
if (State.regs[OP[1]] < State.regs[OP[0]]) if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
{ {
State.regs[OP[0]] = State.regs[OP[1]]; State.regs[OP[0]] = State.regs[OP[1]];
State.F0 = 1; State.F0 = 1;