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RISC-V: Add address printer tests with ADDIW

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Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.

This commit tests whether this sign-extension works.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
	computation with sign extension as used in ADDIW/C.ADDIW.
	* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
	* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.

gas/ChangeLog:

	* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
	* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
	* testsuite/gas/riscv/dis-addr-addiw.s: New test.
This commit is contained in:
Tsukasa OI
2022-08-27 00:10:58 +00:00
committed by Nelson Chu
parent 5edf42b635
commit e9f7ba21f0
3 changed files with 64 additions and 0 deletions
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18
gas/testsuite/gas/riscv/dis-addr-addiw-a.d Normal file
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@ -0,0 +1,18 @@
#as: -march=rv64ic
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0xffffffe0
.*: file format elf64-(little|big)riscv
Disassembly of section .text:
0+ffffffe0 <_start>:
[ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
[ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
[ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
[ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>

18
gas/testsuite/gas/riscv/dis-addr-addiw-b.d Normal file
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#as: -march=rv64ic
#source: dis-addr-addiw.s
#objdump: -d --adjust-vma=0x7fffffe0
.*: file format elf64-(little|big)riscv
Disassembly of section .text:
0+7fffffe0 <_start>:
[ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
[ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
[ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
[ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>

28
gas/testsuite/gas/riscv/dis-addr-addiw.s Normal file
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.set addr_rv64_addiw_0a, 0xfffffffffffffff8 # 0xffffffe0 + 0x18 (sext:32->64)
.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc # 0xfffffff0 + 0x0c (sext:32->64)
.set addr_rv64_addiw_0b, 0x00000004 # 0xffffffe8 + 0x1c
.set addr_rv64_c_addiw_0b, 0x00000008 # 0xfffffff6 + 0x12
.set addr_rv64_addiw_1a, 0x7ffffff8 # 0x7fffffe0 + 0x18
.set addr_rv64_c_addiw_1a, 0x7ffffffc # 0x7ffffff0 + 0x0c
.set addr_rv64_addiw_1b, 0xffffffff80000004 # 0x7fffffe8 + 0x1c (sext:32->64)
.set addr_rv64_c_addiw_1b, 0xffffffff80000008 # 0x7ffffff6 + 0x12 (sext:32->64)
.text
.global _start
_start:
.option push
.option arch, -c
# _start + 0x00
auipc t0, 0
addiw t1, t0, 0x18
# _start + 0x08
auipc t2, 0
addiw t3, t2, 0x1c
.option pop
# _start + 0x10
auipc t4, 0
c.addiw t4, 0x0c
# _start + 0x16
auipc t5, 0
c.addiw t5, 0x12