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RISC-V: Add missing hint instructions from RV128I.

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gas/
	* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test.  Add disabled
	future test for RV128 support.
	* testsuite/gas/riscv/c-zero-reg.s: Likewise.

	include/
	* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
	(MATCH_C_SRAI64, MASK_C_SRAI64): New.
	(MATCH_C_SLLI64, MASK_C_SLLI64): New.

	opcodes/
	* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
	(match_c_slli64, match_srxi_as_c_srxi): New.
	(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
	<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
	<c.slli, c.srli, c.srai>: Use match_s_slli.
	<c.slli64, c.srli64, c.srai64>: New.
This commit is contained in:
Jim Wilson
2018-05-08 15:46:19 -07:00
parent 7402fbcae1
commit e6f372ba66
9 changed files with 92 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/opcode/riscv-opc.h
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@ -459,8 +459,12 @@
#define MASK_C_LUI 0xe003
#define MATCH_C_SRLI 0x8001
#define MASK_C_SRLI 0xec03
#define MATCH_C_SRLI64 0x8001
#define MASK_C_SRLI64 0xfc7f
#define MATCH_C_SRAI 0x8401
#define MASK_C_SRAI 0xec03
#define MATCH_C_SRAI64 0x8401
#define MASK_C_SRAI64 0xfc7f
#define MATCH_C_ANDI 0x8801
#define MASK_C_ANDI 0xec03
#define MATCH_C_SUB 0x8c01
@ -483,6 +487,8 @@
#define MASK_C_BNEZ 0xe003
#define MATCH_C_SLLI 0x2
#define MASK_C_SLLI 0xe003
#define MATCH_C_SLLI64 0x2
#define MASK_C_SLLI64 0xf07f
#define MATCH_C_FLDSP 0x2002
#define MASK_C_FLDSP 0xe003
#define MATCH_C_LWSP 0x4002