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include/opcode/

Browse Source 
2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.

opcodes/

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

gas/testsuite/

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* gas/aarch64/alias.s: Add new tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
This commit is contained in:
Yufeng Zhang
2013-01-30 15:43:32 +00:00
parent f9b2d5449a
commit e30181a58d
14 changed files with 817 additions and 663 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 Markos Chandras <markos.chandras@imgtec.com> 2013-01-30 Markos Chandras <markos.chandras@imgtec.com>
* gas/metag/metacore21-invalid.s: Add invalid SWAP testcases. * gas/metag/metacore21-invalid.s: Add invalid SWAP testcases.

24
gas/testsuite/gas/aarch64/alias.d
View File

@ -72,3 +72,27 @@ Disassembly of section \.text:
100: b13ffdff cmn x15, #0xfff 100: b13ffdff cmn x15, #0xfff
104: f13fffef subs x15, sp, #0xfff 104: f13fffef subs x15, sp, #0xfff
108: b13ffdff cmn x15, #0xfff 108: b13ffdff cmn x15, #0xfff
10c: 0f08a448 sxtl v8.8h, v2.8b
110: 0f08a448 sxtl v8.8h, v2.8b
114: 4f08a448 sxtl2 v8.8h, v2.16b
118: 4f08a448 sxtl2 v8.8h, v2.16b
11c: 0f10a448 sxtl v8.4s, v2.4h
120: 0f10a448 sxtl v8.4s, v2.4h
124: 4f10a448 sxtl2 v8.4s, v2.8h
128: 4f10a448 sxtl2 v8.4s, v2.8h
12c: 0f20a448 sxtl v8.2d, v2.2s
130: 0f20a448 sxtl v8.2d, v2.2s
134: 4f20a448 sxtl2 v8.2d, v2.4s
138: 4f20a448 sxtl2 v8.2d, v2.4s
13c: 2f08a448 uxtl v8.8h, v2.8b
140: 2f08a448 uxtl v8.8h, v2.8b
144: 6f08a448 uxtl2 v8.8h, v2.16b
148: 6f08a448 uxtl2 v8.8h, v2.16b
14c: 2f10a448 uxtl v8.4s, v2.4h
150: 2f10a448 uxtl v8.4s, v2.4h
154: 6f10a448 uxtl2 v8.4s, v2.8h
158: 6f10a448 uxtl2 v8.4s, v2.8h
15c: 2f20a448 uxtl v8.2d, v2.2s
160: 2f20a448 uxtl v8.2d, v2.2s
164: 6f20a448 uxtl2 v8.2d, v2.4s
168: 6f20a448 uxtl2 v8.2d, v2.4s

20
gas/testsuite/gas/aarch64/alias.s
View File

@ -2,7 +2,7 @@
preference. It is also used to test the -Mno-aliases option in preference. It is also used to test the -Mno-aliases option in
the disassemler. the disassemler.
Copyright 2012 Free Software Foundation, Inc. Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of GAS. This file is part of GAS.
@ -99,3 +99,21 @@
adds xzr, x15, #0xfff adds xzr, x15, #0xfff
subs x15, sp, #0xfff subs x15, sp, #0xfff
cmn x15, #0xfff cmn x15, #0xfff
.macro asimdshll s
\s\()xtl v8.8h, v2.8b
\s\()shll v8.8h, v2.8b, #0
\s\()xtl2 v8.8h, v2.16b
\s\()shll2 v8.8h, v2.16b, #0
\s\()xtl v8.4s, v2.4h
\s\()shll v8.4s, v2.4h, #0
\s\()xtl2 v8.4s, v2.8h
\s\()shll2 v8.4s, v2.8h, #0
\s\()xtl v8.2d, v2.2s
\s\()shll v8.2d, v2.2s, #0
\s\()xtl2 v8.2d, v2.4s
\s\()shll2 v8.2d, v2.4s, #0
.endm
asimdshll s
asimdshll u

24
gas/testsuite/gas/aarch64/no-aliases.d
View File

@ -73,3 +73,27 @@ Disassembly of section \.text:
100: b13ffdff adds xzr, x15, #0xfff 100: b13ffdff adds xzr, x15, #0xfff
104: f13fffef subs x15, sp, #0xfff 104: f13fffef subs x15, sp, #0xfff
108: b13ffdff adds xzr, x15, #0xfff 108: b13ffdff adds xzr, x15, #0xfff
10c: 0f08a448 sshll v8.8h, v2.8b, #0
110: 0f08a448 sshll v8.8h, v2.8b, #0
114: 4f08a448 sshll2 v8.8h, v2.16b, #0
118: 4f08a448 sshll2 v8.8h, v2.16b, #0
11c: 0f10a448 sshll v8.4s, v2.4h, #0
120: 0f10a448 sshll v8.4s, v2.4h, #0
124: 4f10a448 sshll2 v8.4s, v2.8h, #0
128: 4f10a448 sshll2 v8.4s, v2.8h, #0
12c: 0f20a448 sshll v8.2d, v2.2s, #0
130: 0f20a448 sshll v8.2d, v2.2s, #0
134: 4f20a448 sshll2 v8.2d, v2.4s, #0
138: 4f20a448 sshll2 v8.2d, v2.4s, #0
13c: 2f08a448 ushll v8.8h, v2.8b, #0
140: 2f08a448 ushll v8.8h, v2.8b, #0
144: 6f08a448 ushll2 v8.8h, v2.16b, #0
148: 6f08a448 ushll2 v8.8h, v2.16b, #0
14c: 2f10a448 ushll v8.4s, v2.4h, #0
150: 2f10a448 ushll v8.4s, v2.4h, #0
154: 6f10a448 ushll2 v8.4s, v2.8h, #0
158: 6f10a448 ushll2 v8.4s, v2.8h, #0
15c: 2f20a448 ushll v8.2d, v2.2s, #0
160: 2f20a448 ushll v8.2d, v2.2s, #0
164: 6f20a448 ushll2 v8.2d, v2.4s, #0
168: 6f20a448 ushll2 v8.2d, v2.4s, #0

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
PR gas/15069 PR gas/15069

7
include/opcode/aarch64.h
View File

@ -1,6 +1,6 @@
/* AArch64 assembler/disassembler support. /* AArch64 assembler/disassembler support.
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of GNU Binutils. This file is part of GNU Binutils.
@ -424,6 +424,11 @@ enum aarch64_op
OP_ROR_IMM, OP_ROR_IMM,
OP_SXTL,
OP_SXTL2,
OP_UXTL,
OP_UXTL2,
OP_TOTAL_NUM, /* Pseudo. */ OP_TOTAL_NUM, /* Pseudo. */
}; };

15
opcodes/ChangeLog
View File

@ -1,3 +1,18 @@
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
2013-01-24 Nick Clifton <nickc@redhat.com> 2013-01-24 Nick Clifton <nickc@redhat.com>
* v850-dis.c: Add support for e3v5 architecture. * v850-dis.c: Add support for e3v5 architecture.

218
opcodes/aarch64-asm-2.c
View File

@ -1,5 +1,5 @@
/* This file is automatically generated by aarch64-gen. Do not edit! */ /* This file is automatically generated by aarch64-gen. Do not edit! */
/* Copyright 2012 Free Software Foundation, Inc. /* Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of the GNU opcodes library. This file is part of the GNU opcodes library.
@ -76,147 +76,159 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 259: /* mov */ case 259: /* mov */
value = 258; /* --> orr. */ value = 258; /* --> orr. */
break; break;
case 427: /* mov */ case 314: /* sxtl */
value = 426; /* --> dup. */ value = 313; /* --> sshll. */
break; break;
case 494: /* sxtw */ case 316: /* sxtl2 */
case 493: /* sxth */ value = 315; /* --> sshll2. */
case 492: /* sxtb */
case 495: /* asr */
case 491: /* sbfx */
case 490: /* sbfiz */
value = 489; /* --> sbfm. */
break; break;
case 498: /* bfxil */ case 336: /* uxtl */
case 497: /* bfi */ value = 335; /* --> ushll. */
value = 496; /* --> bfm. */
break; break;
case 503: /* uxth */ case 338: /* uxtl2 */
case 502: /* uxtb */ value = 337; /* --> ushll2. */
case 505: /* lsr */
case 504: /* lsl */
case 501: /* ubfx */
case 500: /* ubfiz */
value = 499; /* --> ubfm. */
break; break;
case 523: /* cset */ case 431: /* mov */
case 522: /* cinc */ value = 430; /* --> dup. */
value = 521; /* --> csinc. */
break; break;
case 526: /* csetm */ case 498: /* sxtw */
case 525: /* cinv */ case 497: /* sxth */
value = 524; /* --> csinv. */ case 496: /* sxtb */
case 499: /* asr */
case 495: /* sbfx */
case 494: /* sbfiz */
value = 493; /* --> sbfm. */
break; break;
case 528: /* cneg */ case 502: /* bfxil */
value = 527; /* --> csneg. */ case 501: /* bfi */
value = 500; /* --> bfm. */
break; break;
case 553: /* lsl */ case 507: /* uxth */
value = 552; /* --> lslv. */ case 506: /* uxtb */
case 509: /* lsr */
case 508: /* lsl */
case 505: /* ubfx */
case 504: /* ubfiz */
value = 503; /* --> ubfm. */
break; break;
case 555: /* lsr */ case 527: /* cset */
value = 554; /* --> lsrv. */ case 526: /* cinc */
value = 525; /* --> csinc. */
break; break;
case 557: /* asr */ case 530: /* csetm */
value = 556; /* --> asrv. */ case 529: /* cinv */
value = 528; /* --> csinv. */
break; break;
case 559: /* ror */ case 532: /* cneg */
value = 558; /* --> rorv. */ value = 531; /* --> csneg. */
break; break;
case 561: /* mul */ case 557: /* lsl */
value = 560; /* --> madd. */ value = 556; /* --> lslv. */
break; break;
case 563: /* mneg */ case 559: /* lsr */
value = 562; /* --> msub. */ value = 558; /* --> lsrv. */
break; break;
case 565: /* smull */ case 561: /* asr */
value = 564; /* --> smaddl. */ value = 560; /* --> asrv. */
break; break;
case 567: /* smnegl */ case 563: /* ror */
value = 566; /* --> smsubl. */ value = 562; /* --> rorv. */
break; break;
case 570: /* umull */ case 565: /* mul */
value = 569; /* --> umaddl. */ value = 564; /* --> madd. */
break; break;
case 572: /* umnegl */ case 567: /* mneg */
value = 571; /* --> umsubl. */ value = 566; /* --> msub. */
break; break;
case 583: /* ror */ case 569: /* smull */
value = 582; /* --> extr. */ value = 568; /* --> smaddl. */
break; break;
case 683: /* strb */ case 571: /* smnegl */
value = 681; /* --> sturb. */ value = 570; /* --> smsubl. */
break; break;
case 684: /* ldrb */ case 574: /* umull */
value = 682; /* --> ldurb. */ value = 573; /* --> umaddl. */
break; break;
case 686: /* ldrsb */ case 576: /* umnegl */
value = 685; /* --> ldursb. */ value = 575; /* --> umsubl. */
break; break;
case 689: /* str */ case 587: /* ror */
value = 687; /* --> stur. */ value = 586; /* --> extr. */
break; break;
case 690: /* ldr */ case 687: /* strb */
value = 688; /* --> ldur. */ value = 685; /* --> sturb. */
break; break;
case 693: /* strh */ case 688: /* ldrb */
value = 691; /* --> sturh. */ value = 686; /* --> ldurb. */
break; break;
case 694: /* ldrh */ case 690: /* ldrsb */
value = 692; /* --> ldurh. */ value = 689; /* --> ldursb. */
break; break;
case 696: /* ldrsh */ case 693: /* str */
value = 695; /* --> ldursh. */ value = 691; /* --> stur. */
break; break;
case 699: /* str */ case 694: /* ldr */
value = 697; /* --> stur. */ value = 692; /* --> ldur. */
break; break;
case 700: /* ldr */ case 697: /* strh */
value = 698; /* --> ldur. */ value = 695; /* --> sturh. */
break; break;
case 702: /* ldrsw */ case 698: /* ldrh */
value = 701; /* --> ldursw. */ value = 696; /* --> ldurh. */
break; break;
case 704: /* prfm */ case 700: /* ldrsh */
value = 703; /* --> prfum. */ value = 699; /* --> ldursh. */
break; break;
case 746: /* bic */ case 703: /* str */
value = 745; /* --> and. */ value = 701; /* --> stur. */
break; break;
case 748: /* mov */ case 704: /* ldr */
value = 747; /* --> orr. */ value = 702; /* --> ldur. */
break; break;
case 751: /* tst */ case 706: /* ldrsw */
value = 750; /* --> ands. */ value = 705; /* --> ldursw. */
break; break;
case 756: /* uxtw */ case 708: /* prfm */
case 755: /* mov */ value = 707; /* --> prfum. */
value = 754; /* --> orr. */
break; break;
case 758: /* mvn */ case 750: /* bic */
value = 757; /* --> orn. */ value = 749; /* --> and. */
break; break;
case 762: /* tst */ case 752: /* mov */
value = 761; /* --> ands. */ value = 751; /* --> orr. */
break; break;
case 765: /* mov */ case 755: /* tst */
value = 764; /* --> movn. */ value = 754; /* --> ands. */
break; break;
case 767: /* mov */ case 760: /* uxtw */
value = 766; /* --> movz. */ case 759: /* mov */
value = 758; /* --> orr. */
break; break;
case 778: /* sevl */ case 762: /* mvn */
case 777: /* sev */ value = 761; /* --> orn. */
case 776: /* wfi */
case 775: /* wfe */
case 774: /* yield */
case 773: /* nop */
value = 772; /* --> hint. */
break; break;
case 787: /* tlbi */ case 766: /* tst */
case 786: /* ic */ value = 765; /* --> ands. */
case 785: /* dc */ break;
case 784: /* at */ case 769: /* mov */
value = 783; /* --> sys. */ value = 768; /* --> movn. */
break;
case 771: /* mov */
value = 770; /* --> movz. */
break;
case 782: /* sevl */
case 781: /* sev */
case 780: /* wfi */
case 779: /* wfe */
case 778: /* yield */
case 777: /* nop */
value = 776; /* --> hint. */
break;
case 791: /* tlbi */
case 790: /* ic */
case 789: /* dc */
case 788: /* at */
value = 787; /* --> sys. */
break; break;
default: return NULL; default: return NULL;
} }

18
opcodes/aarch64-asm.c
View File

@ -1,5 +1,5 @@
/* aarch64-asm.c -- AArch64 assembler support. /* aarch64-asm.c -- AArch64 assembler support.
Copyright 2012 Free Software Foundation, Inc. Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of the GNU opcodes library. This file is part of the GNU opcodes library.
@ -958,6 +958,16 @@ convert_ror_to_extr (aarch64_inst *inst)
copy_operand_info (inst, 2, 1); copy_operand_info (inst, 2, 1);
} }
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
is equivalent to:
USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
static void
convert_xtl_to_shll (aarch64_inst *inst)
{
inst->operands[2].qualifier = inst->operands[1].qualifier;
inst->operands[2].imm.value = 0;
}
/* Convert /* Convert
LSR <Xd>, <Xn>, #<shift> LSR <Xd>, <Xn>, #<shift>
to to
@ -1167,6 +1177,12 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
case OP_ROR_IMM: case OP_ROR_IMM:
convert_ror_to_extr (inst); convert_ror_to_extr (inst);
break; break;
case OP_SXTL:
case OP_SXTL2:
case OP_UXTL:
case OP_UXTL2:
convert_xtl_to_shll (inst);
break;
default: default:
break; break;
} }

1006
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

21
opcodes/aarch64-dis.c
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@ -1,5 +1,5 @@
/* aarch64-dis.c -- AArch64 disassembler. /* aarch64-dis.c -- AArch64 disassembler.
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of the GNU opcodes library. This file is part of the GNU opcodes library.
@ -1478,6 +1478,20 @@ convert_extr_to_ror (aarch64_inst *inst)
return 0; return 0;
} }
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
is equivalent to:
USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
static int
convert_shll_to_xtl (aarch64_inst *inst)
{
if (inst->operands[2].imm.value == 0)
{
inst->operands[2].type = AARCH64_OPND_NIL;
return 1;
}
return 0;
}
/* Convert /* Convert
UBFM <Xd>, <Xn>, #<shift>, #63. UBFM <Xd>, <Xn>, #<shift>, #63.
to to
@ -1731,6 +1745,11 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
return convert_movebitmask_to_mov (inst); return convert_movebitmask_to_mov (inst);
case OP_ROR_IMM: case OP_ROR_IMM:
return convert_extr_to_ror (inst); return convert_extr_to_ror (inst);
case OP_SXTL:
case OP_SXTL2:
case OP_UXTL:
case OP_UXTL2:
return convert_shll_to_xtl (inst);
default: default:
return 0; return 0;
} }

4
opcodes/aarch64-gen.c
View File

@ -1,6 +1,6 @@
/* aarch64-gen.c -- Generate tables and routines for opcode lookup and /* aarch64-gen.c -- Generate tables and routines for opcode lookup and
instruction encoding and decoding. instruction encoding and decoding.
Copyright 2012 Free Software Foundation, Inc. Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of the GNU opcodes library. This file is part of the GNU opcodes library.
@ -1242,7 +1242,7 @@ main (int argc, char **argv)
print_divide_result (decoder_tree); print_divide_result (decoder_tree);
printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n"); printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n");
printf ("/* Copyright 2012 Free Software Foundation, Inc.\n\ printf ("/* Copyright 2012, 2013 Free Software Foundation, Inc.\n\
Contributed by ARM Ltd.\n\ Contributed by ARM Ltd.\n\
\n\ \n\
This file is part of the GNU opcodes library.\n\ This file is part of the GNU opcodes library.\n\

101
opcodes/aarch64-opc-2.c
View File

@ -1,5 +1,5 @@
/* This file is automatically generated by aarch64-gen. Do not edit! */ /* This file is automatically generated by aarch64-gen. Do not edit! */
/* Copyright 2012 Free Software Foundation, Inc. /* Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd. Contributed by ARM Ltd.
This file is part of the GNU opcodes library. This file is part of the GNU opcodes library.
@ -119,70 +119,73 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] = static const unsigned op_enum_table [] =
{ {
0, 0,
648, 652,
649,
650,
653, 653,
654, 654,
655,
656,
657, 657,
651,
652,
658, 658,
659, 659,
681, 660,
682, 661,
655,
656,
662,
663,
685, 685,
686,
689,
695,
696,
699,
701,
702,
691, 691,
692, 692,
695, 705,
697, 707,
698, 745,
687, 746,
688, 747,
701, 748,
703,
741,
742,
743,
744,
12, 12,
510,
511,
768,
770,
772,
752,
771,
769,
259,
499,
509,
508,
750,
505,
502,
495,
494,
501,
504,
506, 506,
507, 507,
764, 760,
766,
768,
748,
767,
765,
259,
495,
505,
504,
746,
501,
498,
491,
490,
497,
500,
502,
503,
756,
125,
522,
525,
528,
523,
526, 526,
614, 529,
532,
527,
530,
618,
160, 160,
161, 161,
162, 162,
163, 163,
416, 420,
583, 587,
314,
316,
336,
338,
}; };
/* Given the opcode enumerator OP, return the pointer to the corresponding /* Given the opcode enumerator OP, return the pointer to the corresponding

12
opcodes/aarch64-tbl.h
View File

@ -1534,8 +1534,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
{"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0}, {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
{"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0}, {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
{"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
{"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
{"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0}, {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
@ -1554,8 +1556,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0}, {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
{"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0}, {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0}, {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
{"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0}, {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
{"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
{"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
{"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0}, {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
/* AdvSIMD TBL/TBX. */ /* AdvSIMD TBL/TBX. */