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Fix disassembly of RX zero-offset register indirect instructions.

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opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
This commit is contained in:
Nick Clifton
2015-11-02 14:14:22 +00:00
parent a62e598977
commit e292aa7a95
11 changed files with 560 additions and 480 deletions
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4
include/opcode/ChangeLog
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@ -1,3 +1,7 @@
2015-11-02 Nick Clifton <nickc@redhat.com>
* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Update declaration.

1
include/opcode/rx.h
View File

@ -48,6 +48,7 @@ typedef enum
RX_Operand_Immediate, /* #addend */
RX_Operand_Register, /* Rn */
RX_Operand_Indirect, /* [Rn + addend] */
RX_Operand_Zero_Indirect,/* [Rn] */
RX_Operand_Postinc, /* [Rn+] */
RX_Operand_Predec, /* [-Rn] */
RX_Operand_Condition, /* eq, gtu, etc */