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PR26472, PR26473, PR26474 UBSAN: tc-mips.c shift left UB

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PR 26472
	PR 26473
	PR 26474
	* config/tc-mips.c (operand_reg_mask): Shift 1u left.
	(load_register): Shift 0xffffU left.
This commit is contained in:
Alan Modra
2020-08-31 15:38:25 +09:30
parent 46021a61e4
commit e0fd91ef81
2 changed files with 17 additions and 9 deletions
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8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2020-08-31 Alan Modra <amodra@gmail.com>
PR 26472
PR 26473
PR 26474
* config/tc-mips.c (operand_reg_mask): Shift 1u left.
(load_register): Shift 0xffffU left.
2020-08-31 Alan Modra <amodra@gmail.com> 2020-08-31 Alan Modra <amodra@gmail.com>
PR 26471 PR 26471

18
gas/config/tc-mips.c
View File

@ -4656,7 +4656,7 @@ operand_reg_mask (const struct mips_cl_insn *insn,
if (!(type_mask & (1 << reg_op->reg_type))) if (!(type_mask & (1 << reg_op->reg_type)))
return 0; return 0;
uval = insn_extract_operand (insn, operand); uval = insn_extract_operand (insn, operand);
return 1 << mips_decode_reg_operand (reg_op, uval); return 1u << mips_decode_reg_operand (reg_op, uval);
} }
case OP_REG_PAIR: case OP_REG_PAIR:
@ -4667,28 +4667,28 @@ operand_reg_mask (const struct mips_cl_insn *insn,
if (!(type_mask & (1 << pair_op->reg_type))) if (!(type_mask & (1 << pair_op->reg_type)))
return 0; return 0;
uval = insn_extract_operand (insn, operand); uval = insn_extract_operand (insn, operand);
return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); return (1u << pair_op->reg1_map[uval]) | (1u << pair_op->reg2_map[uval]);
} }
case OP_CLO_CLZ_DEST: case OP_CLO_CLZ_DEST:
if (!(type_mask & (1 << OP_REG_GP))) if (!(type_mask & (1 << OP_REG_GP)))
return 0; return 0;
uval = insn_extract_operand (insn, operand); uval = insn_extract_operand (insn, operand);
return (1 << (uval & 31)) | (1 << (uval >> 5)); return (1u << (uval & 31)) | (1u << (uval >> 5));
case OP_SAME_RS_RT: case OP_SAME_RS_RT:
if (!(type_mask & (1 << OP_REG_GP))) if (!(type_mask & (1 << OP_REG_GP)))
return 0; return 0;
uval = insn_extract_operand (insn, operand); uval = insn_extract_operand (insn, operand);
gas_assert ((uval & 31) == (uval >> 5)); gas_assert ((uval & 31) == (uval >> 5));
return 1 << (uval & 31); return 1u << (uval & 31);
case OP_CHECK_PREV: case OP_CHECK_PREV:
case OP_NON_ZERO_REG: case OP_NON_ZERO_REG:
if (!(type_mask & (1 << OP_REG_GP))) if (!(type_mask & (1 << OP_REG_GP)))
return 0; return 0;
uval = insn_extract_operand (insn, operand); uval = insn_extract_operand (insn, operand);
return 1 << (uval & 31); return 1u << (uval & 31);
case OP_LWM_SWM_LIST: case OP_LWM_SWM_LIST:
abort (); abort ();
@ -4703,12 +4703,12 @@ operand_reg_mask (const struct mips_cl_insn *insn,
vsel = uval >> 5; vsel = uval >> 5;
if ((vsel & 0x18) == 0x18) if ((vsel & 0x18) == 0x18)
return 0; return 0;
return 1 << (uval & 31); return 1u << (uval & 31);
case OP_REG_INDEX: case OP_REG_INDEX:
if (!(type_mask & (1 << OP_REG_GP))) if (!(type_mask & (1 << OP_REG_GP)))
return 0; return 0;
return 1 << insn_extract_operand (insn, operand); return 1u << insn_extract_operand (insn, operand);
} }
abort (); abort ();
} }
@ -9564,11 +9564,11 @@ load_register (int reg, expressionS *ep, int dbl)
if (shift < 32) if (shift < 32)
{ {
himask = 0xffff >> (32 - shift); himask = 0xffff >> (32 - shift);
lomask = (0xffff << shift) & 0xffffffff; lomask = (0xffffU << shift) & 0xffffffff;
} }
else else
{ {
himask = 0xffff << (shift - 32); himask = 0xffffU << (shift - 32);
lomask = 0; lomask = 0;
} }
if ((hi32.X_add_number & ~(offsetT) himask) == 0 if ((hi32.X_add_number & ~(offsetT) himask) == 0