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sim/h8300/ChangeLog:
2003-07-23 Richard Sandiford <rsandifo@redhat.com> * compile.c (sim_resume): Make sure that dst.reg refers to the right register byte in mova/sz.l @(dd,RnL),ERn. 2003-07-21 Richard Sandiford <rsandifo@redhat.com> * compile.c (sim_resume): Zero-extend immediate to muls, mulsu, mulxs, divs and divxs. sim/testsuite/sim/h8300/ChangeLog: 2003-07-22 Michael Snyder <msnyder@redhat.com> * mul.s: Don't try to use negative immediate (it's always unsigned). * div.s: Ditto.
This commit is contained in:
Alexandre Oliva
@ -1,5 +1,12 @@
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2004-06-28 Alexandre Oliva <aoliva@redhat.com>
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2003-07-23 Richard Sandiford <rsandifo@redhat.com>
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* compile.c (sim_resume): Make sure that dst.reg refers to the
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right register byte in mova/sz.l @(dd,RnL),ERn.
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2003-07-21 Richard Sandiford <rsandifo@redhat.com>
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* compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
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mulxs, divs and divxs.
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* compile.c (sim_load): Update sd->memory_size.
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2004-06-10 Michael Snyder <msnyder@redhat.com>
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@ -2037,7 +2037,10 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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code->op3.literal = 0;
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if (OP_KIND (code->src.type) == OP_INDEXB)
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code->dst.type = X (OP_REG, SB);
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{
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code->dst.type = X (OP_REG, SB);
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code->dst.reg = code->op3.reg + 8;
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}
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else
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code->dst.type = X (OP_REG, SW);
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}
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@ -3886,13 +3889,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfff0;
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else
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ea = SEXTSHORT (ea);
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ea = SEXTSHORT (ea);
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res = SEXTSHORT (ea * SEXTSHORT (rd));
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n = res & 0x8000;
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@ -3907,11 +3904,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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res = ea * rd;
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n = res & 0x80000000;
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@ -3925,11 +3917,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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/* Compute upper 32 bits of the 64-bit result. */
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res = (((long long) ea) * ((long long) rd)) >> 32;
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@ -3985,13 +3972,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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else
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ea = SEXTCHAR (ea);
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ea = SEXTCHAR (ea);
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res = ea * SEXTCHAR (rd);
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n = res & 0x8000;
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@ -4006,13 +3987,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfff0;
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else
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ea = SEXTSHORT (ea);
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ea = SEXTSHORT (ea);
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res = ea * SEXTSHORT (rd & 0xffff);
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n = res & 0x80000000;
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@ -4103,11 +4078,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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if (ea)
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{
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res = SEXTSHORT (rd) / SEXTSHORT (ea);
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@ -4129,11 +4099,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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if (ea)
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{
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res = rd / ea;
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@ -4205,13 +4170,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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goto end;
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rd = SEXTSHORT (rd);
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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else
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ea = SEXTCHAR (ea);
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ea = SEXTCHAR (ea);
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if (ea)
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{
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@ -4236,12 +4195,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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fetch (sd, &code->dst, &rd))
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goto end;
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/* FIXME: is this the right place to be doing sign extend? */
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if (OP_KIND (code->src.type) == OP_IMM &&
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(ea & 8) != 0)
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ea |= 0xfffffff0;
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else
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ea = SEXTSHORT (ea);
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ea = SEXTSHORT (ea);
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if (ea)
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{
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@ -1,3 +1,10 @@
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2004-06-28 Alexandre Oliva <aoliva@redhat.com>
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2003-07-22 Michael Snyder <msnyder@redhat.com>
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* mul.s: Don't try to use negative immediate (it's always
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unsigned).
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* div.s: Ditto.
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2004-06-24 Alexandre Oliva <aoliva@redhat.com>
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2004-06-17 Alexandre Oliva <aoliva@redhat.com>
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@ -41,9 +41,9 @@ divs_w_imm4_reg:
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set_grs_a5a5
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;; divs.w xx:4, rd
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mov.w #32, r1
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mov.w #-32, r1
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set_ccr_zero
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divs.w #-2:4, r1
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divs.w #2:4, r1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -88,9 +88,9 @@ divs_l_imm4_reg:
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set_grs_a5a5
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;; divs.l xx:4, rd
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mov.l #320000, er1
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mov.l #-320000, er1
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set_ccr_zero
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divs.l #-2:4, er1
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divs.l #2:4, er1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -221,9 +221,9 @@ divxs_b_imm4_reg:
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set_grs_a5a5
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;; divxs.b xx:4, rd
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mov.w #32, r1
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mov.w #-32, r1
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set_ccr_zero
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divxs.b #-2:4, r1
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divxs.b #2:4, r1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -41,9 +41,9 @@ muls_w_imm4_reg:
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set_grs_a5a5
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;; muls.w xx:4, rd
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mov.w #32, r1
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mov.w #-32, r1
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set_ccr_zero
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muls.w #-2:4, r1
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muls.w #2:4, r1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -88,9 +88,9 @@ muls_l_imm4_reg:
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set_grs_a5a5
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;; muls.l xx:4, rd
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mov.l #320000, er1
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mov.l #-320000, er1
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set_ccr_zero
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muls.l #-2:4, er1
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muls.l #2:4, er1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -308,9 +308,9 @@ mulxs_b_imm4_reg:
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set_grs_a5a5
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;; mulxs.b xx:4, rd
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mov.w #32, r1
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mov.w #-32, r1
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set_ccr_zero
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mulxs.b #-2:4, r1
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mulxs.b #2:4, r1
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;; test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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@ -408,9 +408,9 @@ mulxu_b_imm4_reg:
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set_grs_a5a5
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;; mulxu.b xx:4, rd
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mov.b #32, r1l
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mov.b #-32, r1l
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set_ccr_zero
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mulxu.b #-2:4, r1
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mulxu.b #2:4, r1
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;; test ccr ; H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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