diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8bb6ae8b5a7..37b3560f32b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2018-08-29  Daniel Cederman  <cederman@gaisler.com>
+
+	* testsuite/gas/sparc/leon.d: New test.
+	* testsuite/gas/sparc/leon.s: New test.
+	* testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
+
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
diff --git a/gas/testsuite/gas/sparc/leon.d b/gas/testsuite/gas/sparc/leon.d
new file mode 100644
index 00000000000..e3cf550ed74
--- /dev/null
+++ b/gas/testsuite/gas/sparc/leon.d
@@ -0,0 +1,13 @@
+#as: -Aleon
+#objdump: -dr
+#name: LEON instructions
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+   0:	83 88 00 10 	pwr  %l0, %psr
+   4:	83 88 00 00 	pwr  %g0, %psr
+   8:	83 88 20 00 	pwr  %g0, %psr
+   c:	83 88 3f ff 	pwr  -1, %psr
diff --git a/gas/testsuite/gas/sparc/leon.s b/gas/testsuite/gas/sparc/leon.s
new file mode 100644
index 00000000000..7b87c474e3a
--- /dev/null
+++ b/gas/testsuite/gas/sparc/leon.s
@@ -0,0 +1,6 @@
+	.text
+foo:
+	pwr	%l0, %psr
+	pwr	%g0, %psr
+	pwr	0, %psr
+	pwr	-1, %psr
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index dcfec404d16..bb5f7295211 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -65,6 +65,7 @@ if [istarget sparc*-*-*] {
         run_dump_test "ticc-imm-reg"
         run_dump_test "v8-movwr-imm"
         run_dump_test "save-args"
+        run_dump_test "leon"
 
 	set_tests_arch "v9c"
 	run_dump_test "ldtxa"
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f536bc43686..bbafb45fdf7 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-08-29  Martin Aberg  <maberg@gaisler.com>
+
+	* sparc-opc.c (sparc_opcodes): Add Leon specific partial write
+        psr (PWRPSR) instruction.
+
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 6de9305d145..ab39398b5b8 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -71,6 +71,7 @@
                          | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
                          | MASK_M8)
 #define sparclet	(MASK_SPARCLET)
+#define leon		(MASK_LEON)
 /* sparclet insns supported by leon.  */
 #define letandleon	(MASK_SPARCLET | MASK_LEON)
 #define sparclite	(MASK_SPARCLITE)
@@ -1023,6 +1024,13 @@ wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr  */
 wrasr (27, HWCAP_PAUSE, 0, v9e),  /* wr ...,%pause  */
 wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait  */
 
+{ "pwr",	F3(2, 0x31, 0)|RD(1),	F3(~2, ~0x31, ~0)|RD(~1)|ASI(~0),		"1,2,p", 0, 0, 0, leon }, /* pwr r,r,%psr */
+{ "pwr",	F3(2, 0x31, 1)|RD(1),	F3(~2, ~0x31, ~1)|RD(~1),			"1,i,p", 0, 0, 0, leon }, /* pwr r,i,%psr */
+{ "pwr",	F3(2, 0x31, 0)|RD(1),	F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|ASI(~0),	"2,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,rs2,%psr */
+{ "pwr",	F3(2, 0x31, 1)|RD(1),	F3(~2, ~0x31, ~1)|RD(~1)|RS1_G0,		"i,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,i,%psr */
+{ "pwr",	F3(2, 0x31, 1)|RD(1),	F3(~2, ~0x31, ~1)|RD(~1)|SIMM13(~0),		"1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,0,%psr */
+{ "pwr",	F3(2, 0x31, 0)|RD(1),	F3(~2, ~0x31, ~0)|RD(~1)|ASI_RS2(~0),		"1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,%g0,%psr */
+
 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */
 
 { "rd",	F3(2, 0x28, 0)|RS1(2),		F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),	"E,d", 0, 0, 0, v9 }, /* rd %ccr,r */