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RISC-V: Add instructions and operand set for z[fdq]inx

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Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
  z*inx extension.

gas/ChangeLog:

* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.

include/ChangeLog:

* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.

opcodes/ChangeLog:

* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
  z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
jiawei
2021-11-17 20:10:07 +08:00
committed by Nelson Chu
parent da05b70e56
commit de83e5142d
5 changed files with 167 additions and 149 deletions
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3
include/opcode/riscv.h
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@ -369,6 +369,9 @@ enum riscv_insn_class
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_F_OR_ZFINX,
INSN_CLASS_D_OR_ZDINX,
INSN_CLASS_Q_OR_ZQINX,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,