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MIPS/opcodes: Add legacy CP1 control register names

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The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly.  Do not update the TX39 though as it did not have an FPU.

	opcodes/
	* mips-dis.c (mips_cp1_names_mips): New variable.
	(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
	for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
	"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
	"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
	"r12000", "r14000", "r16000", "mips5", "loongson2e", and
	"loongson2f".

	gas/
	* testsuite/gas/mips/cp1-names-r3900.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.
	* testsuite/gas/mips/branch-misc-3.d: Update disassembly
	according to changes to opcodes.
	* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
	* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
	* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
	* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
	* testsuite/gas/mips/trunc.d: Likewise.
This commit is contained in:
Maciej W. Rozycki
2021-05-29 03:26:32 +02:00
parent 709aa065e1
commit dd84446824
11 changed files with 94 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

62
opcodes/mips-dis.c
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@ -182,6 +182,18 @@ static const char * const mips_cp0_names_mips3264[32] =
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
static const char * const mips_cp1_names_mips[32] =
{
"c1_fir", "$1", "$2", "$3",
"$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11",
"$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19",
"$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27",
"$28", "$29", "$30", "c1_fcsr"
};
static const char * const mips_cp1_names_mips3264[32] =
{
"c1_fir", "c1_ufr", "$2", "$3",
@ -466,76 +478,76 @@ const struct mips_arch_choice mips_arch_choices[] =
mips_hwr_names_numeric },
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_r3000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric,
mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_r5900, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@ -636,11 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
{ "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
/* The loongson3a is an alias of gs464 for compatibility */
{ "loongson3a", 1, bfd_mach_mips_gs464, CPU_GS464,