PowerPC add initial -mfuture instruction support

This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.

include/
	* dis-asm.h (WIDE_OUTPUT): Define.
	* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
	(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
	(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
	* ppc-dis.c (ppc_opts): Add "future" entry.
	(PREFIX_OPCD_SEGS): Define.
	(prefix_opcd_indices): New array.
	(disassemble_init_powerpc): Initialize prefix_opcd_indices.
	(lookup_prefix): New function.
	(print_insn_powerpc): Handle 64-bit prefix instructions.
	* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
	(PMRR, POWERXX): Define.
	(prefix_opcodes): New instruction table.
	(prefix_num_opcodes): New constant.
binutils/
	* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
	(struct insn_label_list): New.
	(insn_labels, free_insn_labels): New variables.
	(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
	(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
	and call ppc_record_label.
	(md_assemble): Handle 64-bit prefix instructions.  Align labels
	that are on the same line as a prefix instruction.
	* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
	later in the file.
	(md_start_line_hook): Define.
	(ppc_start_line_hook): Declare.
	* testsuite/gas/ppc/prefix-align.d,
	* testsuite/gas/ppc/prefix-align.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run new test.
This commit is contained in:
Peter Bergner
2018-05-15 16:48:14 -05:00
committed by Alan Modra
parent fcb36d7462
commit dd7efa7915
14 changed files with 412 additions and 42 deletions

View File

@ -68,6 +68,8 @@ struct powerpc_opcode
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const unsigned int powerpc_num_opcodes;
extern const struct powerpc_opcode prefix_opcodes[];
extern const unsigned int prefix_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const unsigned int vle_num_opcodes;
extern const struct powerpc_opcode spe2_opcodes[];
@ -226,6 +228,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is supported by EFS2. */
#define PPC_OPCODE_EFS2 0x200000000000ull
/* Opcode is only supported by powerxx architecture. */
#define PPC_OPCODE_POWERXX 0x400000000000ull
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@ -243,6 +248,19 @@ extern const unsigned int spe2_num_opcodes;
/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
/* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
#define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
/* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
#define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
/* A macro to determine whether insn I is an 8-byte prefix instruction. */
#define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
/* A macro used to hash 8-byte PREFIX instructions. */
#define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
/* The operands table is an array of struct powerpc_operand. */