Support fs_base and gs_base on FreeBSD/i386.

The i386 BSD native target uses the same ptrace operations
(PT_[GS]ET[FG]SBASE) as the amd64 BSD native target to fetch and store
the registers.

The amd64 BSD native now uses 'tdep->fsbase_regnum' instead of
hardcoding AMD64_FSBASE_REGNUM and AMD64_GSBASE_REGNUM to support
32-bit targets.  In addition, the store operations explicitly zero the
new register value before fetching it from the register cache to
ensure 32-bit values are zero-extended.

gdb/ChangeLog:

	* amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use
	tdep->fsbase_regnum instead of constants for fs_base and gs_base.
	(amd64bsd_store_inferior_registers): Likewise.
	* amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description):
	Enable segment base registers.
	* i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use
	PT_GETFSBASE and PT_GETGSBASE.
	(i386bsd_store_inferior_registers): Use PT_SETFSBASE and
	PT_SETGSBASE.
	* i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable
	segment base registers.
	* i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise.
This commit is contained in:
John Baldwin
2019-03-12 13:39:02 -07:00
parent 1163a4b7a3
commit dd6876c91c
6 changed files with 91 additions and 12 deletions

View File

@ -160,7 +160,7 @@ i386_fbsd_nat_target::read_description ()
if (x86bsd_xsave_len == 0)
xcr0 = X86_XSTATE_SSE_MASK;
return i386_target_description (xcr0, false);
return i386_target_description (xcr0, true);
}
#endif