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https://github.com/espressif/binutils-gdb.git
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RISC-V: Comments tidy and improvement.
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces. But sometimes it should be more
cleaner when the comments only include a word or codes. Therefore, I made
the following changes after referring to other target/generic codes,
* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.
Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.
bfd/
* elfnn-riscv.c: Comments tidy and improvement.
* elfxx-riscv.c: Likewise.
* elfxx-riscv.h: Likewise.
gas/
* config/tc-riscv.c: Comments tidy and improvement. Also update
comment "fallthru" to "Fall through" that end with a period and
two spaces.
include/
* elf/riscv.h: Comments tidy and improvement.
* opcode/riscv-opc.h: Likewise.
* opcode/riscv.h: Likewise.
opcodes/
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
This commit is contained in:
Nelson Chu
@ -1,3 +1,9 @@
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2021-01-15 Nelson Chu <nelson.chu@sifive.com>
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* elfnn-riscv.c: Comments tidy and improvement.
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* elfxx-riscv.c: Likewise.
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* elfxx-riscv.h: Likewise.
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2021-01-14 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/26688
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@ -133,7 +133,6 @@ struct riscv_elf_link_hash_table
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};
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/* Instruction access functions. */
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#define riscv_get_insn(bits, ptr) \
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((bits) == 16 ? bfd_getl16 (ptr) \
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: (bits) == 32 ? bfd_getl32 (ptr) \
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@ -185,14 +184,11 @@ riscv_is_insn_reloc (const reloc_howto_type *howto)
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}
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/* PLT/GOT stuff. */
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#define PLT_HEADER_INSNS 8
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#define PLT_ENTRY_INSNS 4
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#define PLT_HEADER_SIZE (PLT_HEADER_INSNS * 4)
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#define PLT_ENTRY_SIZE (PLT_ENTRY_INSNS * 4)
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#define GOT_ENTRY_SIZE RISCV_ELF_WORD_BYTES
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/* Reserve two entries of GOTPLT for ld.so, one is used for PLT resolver,
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the other is used for link map. Other targets also reserve one more
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entry used for runtime profile? */
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@ -618,6 +614,7 @@ bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h)
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bfd_set_error (bfd_error_bad_value);
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return FALSE;
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}
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/* Look through the relocs for a section during the first phase, and
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allocate space in the global offset table or procedure linkage
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table. */
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@ -743,8 +740,8 @@ riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
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case R_RISCV_CALL:
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case R_RISCV_CALL_PLT:
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/* These symbol requires a procedure linkage table entry. We
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actually build the entry in adjust_dynamic_symbol,
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/* These symbol requires a procedure linkage table entry.
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We actually build the entry in adjust_dynamic_symbol,
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because these might be a case of linking PIC code without
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linking in any dynamic objects, in which case we don't
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need to generate a procedure linkage table after all. */
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@ -1806,24 +1803,24 @@ riscv_zero_pcrel_hi_reloc (Elf_Internal_Rela *rel,
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bfd *input_bfd ATTRIBUTE_UNUSED)
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{
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/* We may need to reference low addreses in PC-relative modes even when the
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* PC is far away from these addresses. For example, undefweak references
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* need to produce the address 0 when linked. As 0 is far from the arbitrary
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* addresses that we can link PC-relative programs at, the linker can't
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* actually relocate references to those symbols. In order to allow these
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* programs to work we simply convert the PC-relative auipc sequences to
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* 0-relative lui sequences. */
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PC is far away from these addresses. For example, undefweak references
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need to produce the address 0 when linked. As 0 is far from the arbitrary
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addresses that we can link PC-relative programs at, the linker can't
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actually relocate references to those symbols. In order to allow these
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programs to work we simply convert the PC-relative auipc sequences to
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0-relative lui sequences. */
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if (bfd_link_pic (info))
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return FALSE;
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/* If it's possible to reference the symbol using auipc we do so, as that's
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* more in the spirit of the PC-relative relocations we're processing. */
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more in the spirit of the PC-relative relocations we're processing. */
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bfd_vma offset = addr - pc;
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if (ARCH_SIZE == 32 || VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (offset)))
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return FALSE;
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/* If it's impossible to reference this with a LUI-based offset then don't
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* bother to convert it at all so users still see the PC-relative relocation
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* in the truncation message. */
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bother to convert it at all so users still see the PC-relative relocation
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in the truncation message. */
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if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (addr)))
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return FALSE;
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@ -3305,7 +3302,7 @@ riscv_float_abi_string (flagword flags)
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}
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}
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/* The information of architecture attribute. */
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/* The information of architecture elf attributes. */
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static riscv_subset_list_t in_subsets;
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static riscv_subset_list_t out_subsets;
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static riscv_subset_list_t merged_subsets;
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@ -3382,11 +3379,10 @@ riscv_i_or_e_p (bfd *ibfd,
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Arguments:
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`bfd`: bfd handler.
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`in_arch`: Raw arch string for input object.
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`out_arch`: Raw arch string for output object.
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`pin`: subset list for input object, and it'll skip all merged subset after
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merge.
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`pout`: Like `pin`, but for output object. */
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`in_arch`: Raw ISA string for input object.
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`out_arch`: Raw ISA string for output object.
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`pin`: Subset list for input object.
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`pout`: Subset list for output object. */
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static bfd_boolean
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riscv_merge_std_ext (bfd *ibfd,
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@ -3555,7 +3551,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
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if (in_arch != NULL && out_arch == NULL)
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return in_arch;
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/* Parse subset from arch string. */
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/* Parse subset from ISA string. */
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if (!riscv_parse_subset (&rpe_in, in_arch))
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return NULL;
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@ -3660,7 +3656,7 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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else if (in_attr[Tag_RISCV_arch].s
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&& out_attr[Tag_RISCV_arch].s)
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{
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/* Check arch compatible. */
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/* Check compatible. */
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char *merged_arch =
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riscv_merge_arch_attr_info (ibfd,
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in_attr[Tag_RISCV_arch].s,
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@ -3678,7 +3674,7 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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case Tag_RISCV_priv_spec:
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case Tag_RISCV_priv_spec_minor:
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case Tag_RISCV_priv_spec_revision:
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/* If we have handled the priv attributes, then skip it. */
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/* If we have handled the privileged elf attributes, then skip it. */
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if (!priv_attrs_merged)
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{
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unsigned int Tag_a = Tag_RISCV_priv_spec;
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@ -3687,7 +3683,7 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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enum riscv_priv_spec_class in_priv_spec;
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enum riscv_priv_spec_class out_priv_spec;
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/* Get the priv spec class from elf attribute numbers. */
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/* Get the privileged spec class from elf attributes. */
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riscv_get_priv_spec_class_from_numbers (in_attr[Tag_a].i,
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in_attr[Tag_b].i,
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in_attr[Tag_c].i,
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@ -3697,7 +3693,7 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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out_attr[Tag_c].i,
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&out_priv_spec);
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/* Allow to link the object without the priv specs. */
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/* Allow to link the object without the privileged specs. */
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if (out_priv_spec == PRIV_SPEC_CLASS_NONE)
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{
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out_attr[Tag_a].i = in_attr[Tag_a].i;
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@ -3718,10 +3714,9 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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out_attr[Tag_b].i,
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out_attr[Tag_c].i);
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/* The priv spec v1.9.1 can not be linked with other spec
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versions since the conflicts. We plan to drop the
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v1.9.1 in a year or two, so this confict should be
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removed in the future. */
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/* The privileged spec v1.9.1 can not be linked with others
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since the conflicts, so we plan to drop it in a year or
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two. */
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if (in_priv_spec == PRIV_SPEC_CLASS_1P9P1
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|| out_priv_spec == PRIV_SPEC_CLASS_1P9P1)
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{
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@ -3730,7 +3725,7 @@ riscv_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
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"linked with other spec versions"));
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}
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/* Update the output priv spec to the newest one. */
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/* Update the output privileged spec to the newest one. */
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if (in_priv_spec > out_priv_spec)
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{
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out_attr[Tag_a].i = in_attr[Tag_a].i;
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@ -3938,8 +3933,9 @@ riscv_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, size_t count,
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call to SYMBOL as well. Since both __wrap_SYMBOL and SYMBOL reference
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the same symbol (which is __wrap_SYMBOL), but still exist as two
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different symbols in 'sym_hashes', we don't want to adjust
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the global symbol __wrap_SYMBOL twice. */
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/* The same problem occurs with symbols that are versioned_hidden, as
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the global symbol __wrap_SYMBOL twice.
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The same problem occurs with symbols that are versioned_hidden, as
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foo becomes an alias for foo@BAR, and hence they need the same
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treatment. */
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if (link_info->wrap_hash != NULL
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@ -4177,9 +4173,9 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
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r_type = R_RISCV_JAL;
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auipc = MATCH_JAL | (rd << OP_SH_RD);
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}
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else /* near_zero */
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else
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{
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/* Relax to JALR rd, x0, addr. */
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/* Near zero, relax to JALR rd, x0, addr. */
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r_type = R_RISCV_LO12_I;
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auipc = MATCH_JALR | (rd << OP_SH_RD);
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}
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@ -4212,7 +4208,7 @@ _bfd_riscv_get_max_alignment (asection *sec)
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return (bfd_vma) 1 << max_alignment_power;
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}
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/* Relax non-PIC global variable references. */
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/* Relax non-PIC global variable references to GP-relative references. */
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static bfd_boolean
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_bfd_riscv_relax_lui (bfd *abfd,
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@ -4325,7 +4321,7 @@ _bfd_riscv_relax_lui (bfd *abfd,
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return TRUE;
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}
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/* Relax non-PIC TLS references. */
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/* Relax non-PIC TLS references to TP-relative references. */
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static bfd_boolean
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_bfd_riscv_relax_tls_le (bfd *abfd,
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@ -4446,7 +4442,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
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BFD_ASSERT (rel->r_offset + 4 <= sec->size);
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/* Chain the _LO relocs to their cooresponding _HI reloc to compute the
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* actual target address. */
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actual target address. */
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riscv_pcgp_hi_reloc hi_reloc;
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memset (&hi_reloc, 0, sizeof (hi_reloc));
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switch (ELFNN_R_TYPE (rel->r_info))
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@ -4486,7 +4482,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
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return TRUE;
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/* If the cooresponding lo relocation has already been seen then it's not
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* safe to relax this relocation. */
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safe to relax this relocation. */
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if (riscv_find_pcgp_lo_reloc (pcgp_relocs, rel->r_offset))
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return TRUE;
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@ -4577,7 +4573,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
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return TRUE;
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}
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/* Relax PC-relative references to GP-relative references. */
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/* Delete the bytes for R_RISCV_DELETE. */
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static bfd_boolean
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_bfd_riscv_relax_delete (bfd *abfd,
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@ -4599,9 +4595,12 @@ _bfd_riscv_relax_delete (bfd *abfd,
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return TRUE;
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}
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/* Relax a section. Pass 0 shortens code sequences unless disabled. Pass 1
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deletes the bytes that pass 0 made obselete. Pass 2, which cannot be
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disabled, handles code alignment directives. */
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/* Relax a section.
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|
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Pass 0: Shortens code sequences for LUI/CALL/TPREL relocs.
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Pass 1: Shortens code sequences for PCREL relocs.
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Pass 2: Deletes the bytes that pass 1 made obselete.
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Pass 3: Which cannot be disabled, handles code alignment directives. */
|
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|
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static bfd_boolean
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_bfd_riscv_relax_section (bfd *abfd, asection *sec,
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@ -4953,6 +4952,7 @@ riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
|
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}
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|
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/* Set the right mach type. */
|
||||
|
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static bfd_boolean
|
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riscv_elf_object_p (bfd *abfd)
|
||||
{
|
||||
|
||||
@ -872,7 +872,6 @@ static reloc_howto_type howto_table[] =
|
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};
|
||||
|
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/* A mapping from BFD reloc types to RISC-V ELF reloc types. */
|
||||
|
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struct elf_reloc_map
|
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{
|
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bfd_reloc_code_real_type bfd_val;
|
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@ -1025,11 +1024,11 @@ riscv_elf_add_sub_reloc (bfd *abfd,
|
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return bfd_reloc_ok;
|
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}
|
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|
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/* Array is used to compare the all extensions' order quickly.
|
||||
/* Array is used to compare the orders of all extensions quickly.
|
||||
|
||||
Zero number means it is a preserved keyword.
|
||||
Negative number means it is a prefix keyword (s, h, x, z).
|
||||
Positive number means it is a standard extension. */
|
||||
Zero value: Preserved keyword.
|
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Negative value: Prefixed keyword (s, h, x, z).
|
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Positive value: Standard extension. */
|
||||
|
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static int riscv_ext_order[26] = {0};
|
||||
|
||||
@ -1093,7 +1092,7 @@ riscv_lookup_subset (const riscv_subset_list_t *subset_list,
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Add arch string extension to the last of the subset list. */
|
||||
/* Add extension from ISA string to the last of the subset list. */
|
||||
|
||||
void
|
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riscv_add_subset (riscv_subset_list_t *subset_list,
|
||||
@ -1150,7 +1149,7 @@ riscv_add_implicit_subset (riscv_subset_list_t *subset_list,
|
||||
|
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/* These extensions are added to the subset list for special purposes,
|
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with the explicit versions or the RISCV_UNKNOWN_VERSION versions.
|
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Therefore, we won't output them to the output arch string in the
|
||||
Therefore, we won't output them to the output ISA string in the
|
||||
riscv_arch_str1, if the versions are unknown. */
|
||||
|
||||
static bfd_boolean
|
||||
@ -1163,8 +1162,8 @@ riscv_ext_dont_care_version (const char *subset)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* We have to add all arch string extensions first, and then start to
|
||||
add their implicit extensions. The arch string extensions must be
|
||||
/* We have to add all extensions from ISA string first, and then start to
|
||||
add their implicit extensions. The extensions from ISA string must be
|
||||
set in order, so we can add them to the last of the subset list
|
||||
directly, without searching.
|
||||
|
||||
@ -1238,7 +1237,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list)
|
||||
|
||||
Arguments:
|
||||
`rps`: Hooks and status for parsing extensions.
|
||||
`march`: Full arch string.
|
||||
`march`: Full ISA string.
|
||||
`p`: Curent parsing position.
|
||||
`major_version`: Parsed major version.
|
||||
`minor_version`: Parsed minor version.
|
||||
@ -1323,7 +1322,7 @@ riscv_supported_std_ext (void)
|
||||
|
||||
Arguments:
|
||||
`rps`: Hooks and status for parsing extensions.
|
||||
`march`: Full arch string.
|
||||
`march`: Full ISA string.
|
||||
`p`: Curent parsing position. */
|
||||
|
||||
static const char *
|
||||
@ -1379,7 +1378,7 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
|
||||
RISCV_UNKNOWN_VERSION,
|
||||
RISCV_UNKNOWN_VERSION, FALSE);
|
||||
/* g-ext is used to add the implicit extensions, but will
|
||||
not be output to the arch string. */
|
||||
not be output to the ISA string. */
|
||||
riscv_parse_add_subset (rps, "g",
|
||||
major_version,
|
||||
minor_version, FALSE);
|
||||
@ -1441,7 +1440,7 @@ riscv_parse_std_ext (riscv_parse_subset_t *rps,
|
||||
return p;
|
||||
}
|
||||
|
||||
/* Classify the argument 'arch' into one of riscv_isa_ext_class_t. */
|
||||
/* Classify ARCH into one of riscv_isa_ext_class_t. */
|
||||
|
||||
riscv_isa_ext_class_t
|
||||
riscv_get_prefix_class (const char *arch)
|
||||
@ -1459,7 +1458,6 @@ riscv_get_prefix_class (const char *arch)
|
||||
/* Structure describing parameters to use when parsing a particular
|
||||
riscv_isa_ext_class_t. One of these should be provided for each
|
||||
possible class, except RV_ISA_CLASS_UNKNOWN. */
|
||||
|
||||
typedef struct riscv_parse_config
|
||||
{
|
||||
/* Class of the extension. */
|
||||
@ -1481,7 +1479,7 @@ typedef struct riscv_parse_config
|
||||
|
||||
Arguments:
|
||||
`rps`: Hooks and status for parsing extensions.
|
||||
`march`: Full architecture string.
|
||||
`march`: Full ISA string.
|
||||
`p`: Curent parsing position.
|
||||
`config`: What class and predicate function to use for the
|
||||
extension. */
|
||||
@ -1667,7 +1665,6 @@ riscv_ext_h_valid_p (const char *arg)
|
||||
|
||||
/* Parsing order of the prefixed extensions that is specified by
|
||||
the ISA spec. */
|
||||
|
||||
static const riscv_parse_config_t parse_config[] =
|
||||
{
|
||||
{RV_ISA_CLASS_S, "s", riscv_ext_s_valid_p},
|
||||
@ -1692,7 +1689,7 @@ riscv_init_ext_order (void)
|
||||
if (inited)
|
||||
return;
|
||||
|
||||
/* All standard extensions' orders are positive numbers. */
|
||||
/* The orders of all standard extensions are positive. */
|
||||
order = 1;
|
||||
|
||||
/* Init the standard base extensions first. */
|
||||
@ -1703,8 +1700,7 @@ riscv_init_ext_order (void)
|
||||
for (ext = std_remain_exts; *ext; ext++)
|
||||
riscv_ext_order[(*ext - 'a')] = order++;
|
||||
|
||||
/* Init the order for prefixed keywords. The orders are
|
||||
negative numbers. */
|
||||
/* Init the order for prefixed keywords. The orders are negative. */
|
||||
order = -1;
|
||||
for (i = 0; parse_config[i].class != RV_ISA_CLASS_UNKNOWN; i++)
|
||||
{
|
||||
@ -1715,7 +1711,7 @@ riscv_init_ext_order (void)
|
||||
inited = TRUE;
|
||||
}
|
||||
|
||||
/* Add the implicit extensions according to the arch string extensions. */
|
||||
/* Add the implicit extensions. */
|
||||
|
||||
static void
|
||||
riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
|
||||
@ -1773,14 +1769,14 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
|
||||
}
|
||||
}
|
||||
|
||||
/* Function for parsing arch string.
|
||||
/* Function for parsing ISA string.
|
||||
|
||||
Return Value:
|
||||
Return TRUE on success.
|
||||
|
||||
Arguments:
|
||||
`rps`: Hooks and status for parsing extensions.
|
||||
`arch`: Full arch string. */
|
||||
`arch`: Full ISA string. */
|
||||
|
||||
bfd_boolean
|
||||
riscv_parse_subset (riscv_parse_subset_t *rps,
|
||||
@ -1815,11 +1811,11 @@ riscv_parse_subset (riscv_parse_subset_t *rps,
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Arch string shouldn't be NULL or empty here. However,
|
||||
it might be empty only when we failed to merge the arch
|
||||
/* ISA string shouldn't be NULL or empty here. However,
|
||||
it might be empty only when we failed to merge the ISA
|
||||
string in the riscv_merge_attributes. We have already
|
||||
issued the correct error message in another side, so do
|
||||
not issue this error when the arch string is empty. */
|
||||
not issue this error when the ISA string is empty. */
|
||||
if (strlen (arch))
|
||||
rps->error_handler (
|
||||
_("-march=%s: ISA string must begin with rv32 or rv64"),
|
||||
@ -1903,7 +1899,7 @@ riscv_estimate_arch_strlen1 (const riscv_subset_t *subset)
|
||||
return riscv_estimate_arch_strlen1 (subset->next)
|
||||
+ strlen (subset->name)
|
||||
+ riscv_estimate_digit (subset->major_version)
|
||||
+ 1 /* For version seperator: 'p'. */
|
||||
+ 1 /* For version seperator 'p'. */
|
||||
+ riscv_estimate_digit (subset->minor_version)
|
||||
+ 1 /* For underscore. */;
|
||||
}
|
||||
@ -1953,7 +1949,7 @@ riscv_arch_str1 (riscv_subset_t *subset,
|
||||
riscv_arch_str1 (subset_t->next, attr_str, buf, bufsz);
|
||||
}
|
||||
|
||||
/* Convert subset info to string with explicit version info. */
|
||||
/* Convert subset information into string with explicit versions. */
|
||||
|
||||
char *
|
||||
riscv_arch_str (unsigned xlen, const riscv_subset_list_t *subset)
|
||||
|
||||
@ -90,9 +90,7 @@ riscv_arch_str (unsigned, const riscv_subset_list_t *);
|
||||
extern size_t
|
||||
riscv_estimate_digit (unsigned);
|
||||
|
||||
/* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z,
|
||||
"xargs" corresponds to RV_ISA_CLASS_X, etc. */
|
||||
|
||||
/* ISA extension prefixed name class. */
|
||||
typedef enum riscv_isa_ext_class
|
||||
{
|
||||
RV_ISA_CLASS_S,
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
|
||||
|
||||
* config/tc-riscv.c: Comments tidy and improvement. Also update
|
||||
comment "fallthru" to "Fall through" that end with a period and
|
||||
two spaces.
|
||||
|
||||
2021-01-14 Mike Frysinger <vapier@gentoo.org>
|
||||
|
||||
* doc/as.texi: Delete @ifset ELF wrapping around [248]byte entries.
|
||||
|
||||
@ -64,17 +64,11 @@ struct riscv_cl_insn
|
||||
#endif
|
||||
|
||||
/* Let riscv_after_parse_args set the default value according to xlen. */
|
||||
|
||||
#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
|
||||
#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
|
||||
#endif
|
||||
|
||||
/* The default ISA spec is set to 2.2 rather than the lastest version.
|
||||
The reason is that compiler generates the ISA string with fixed 2p0
|
||||
verisons only for the RISCV ELF architecture attributes, but not for
|
||||
the -march option. Therefore, we should update the compiler or linker
|
||||
to resolve this problem. */
|
||||
|
||||
/* Need to sync the version with RISC-V compiler. */
|
||||
#ifndef DEFAULT_RISCV_ISA_SPEC
|
||||
#define DEFAULT_RISCV_ISA_SPEC "2.2"
|
||||
#endif
|
||||
@ -88,8 +82,8 @@ static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
|
||||
static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
|
||||
static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
|
||||
|
||||
static unsigned xlen = 0; /* width of an x-register */
|
||||
static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
|
||||
static unsigned xlen = 0; /* The width of an x-register. */
|
||||
static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
|
||||
static bfd_boolean rve_abi = FALSE;
|
||||
enum float_abi {
|
||||
FLOAT_ABI_DEFAULT = -1,
|
||||
@ -105,8 +99,8 @@ static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
|
||||
|
||||
static unsigned elf_flags = 0;
|
||||
|
||||
/* Set the default_isa_spec. Return 0 if the input spec string isn't
|
||||
supported. Otherwise, return 1. */
|
||||
/* Set the default_isa_spec. Return 0 if the spec isn't supported.
|
||||
Otherwise, return 1. */
|
||||
|
||||
static int
|
||||
riscv_set_default_isa_spec (const char *s)
|
||||
@ -123,10 +117,9 @@ riscv_set_default_isa_spec (const char *s)
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Set the default_priv_spec, assembler will find the suitable CSR address
|
||||
according to default_priv_spec. We will try to check priv attributes if
|
||||
the input string is NULL. Return 0 if the input priv spec string isn't
|
||||
supported. Otherwise, return 1. */
|
||||
/* Set the default_priv_spec. Find the privileged elf attributes when
|
||||
the input string is NULL. Return 0 if the spec isn't supported.
|
||||
Otherwise, return 1. */
|
||||
|
||||
static int
|
||||
riscv_set_default_priv_spec (const char *s)
|
||||
@ -135,7 +128,6 @@ riscv_set_default_priv_spec (const char *s)
|
||||
unsigned major, minor, revision;
|
||||
obj_attribute *attr;
|
||||
|
||||
/* Find the corresponding priv spec class. */
|
||||
if (riscv_get_priv_spec_class (s, &class))
|
||||
{
|
||||
default_priv_spec = class;
|
||||
@ -149,20 +141,17 @@ riscv_set_default_priv_spec (const char *s)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Try to set the default_priv_spec according to the priv attributes. */
|
||||
/* Set the default_priv_spec by the privileged elf attributes. */
|
||||
attr = elf_known_obj_attributes_proc (stdoutput);
|
||||
major = (unsigned) attr[Tag_RISCV_priv_spec].i;
|
||||
minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
|
||||
revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
|
||||
|
||||
if (riscv_get_priv_spec_class_from_numbers (major,
|
||||
minor,
|
||||
revision,
|
||||
&class))
|
||||
{
|
||||
/* The priv attributes setting 0.0.0 is meaningless. We should have set
|
||||
the default_priv_spec by md_parse_option and riscv_after_parse_args,
|
||||
so just skip the following setting. */
|
||||
/* 0.0.0 is meaningless. */
|
||||
if (class == PRIV_SPEC_CLASS_NONE)
|
||||
return 1;
|
||||
|
||||
@ -170,21 +159,20 @@ riscv_set_default_priv_spec (const char *s)
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Still can not find the priv spec class. */
|
||||
/* Still can not find the privileged spec class. */
|
||||
as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
|
||||
"privilege attributes"), major, minor, revision);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This is the set of options which the .option pseudo-op may modify. */
|
||||
|
||||
struct riscv_set_options
|
||||
{
|
||||
int pic; /* Generate position-independent code. */
|
||||
int rvc; /* Generate RVC code. */
|
||||
int rve; /* Generate RVE code. */
|
||||
int relax; /* Emit relocs the linker is allowed to relax. */
|
||||
int arch_attr; /* Emit arch attribute. */
|
||||
int arch_attr; /* Emit architecture and privileged elf attributes. */
|
||||
int csr_check; /* Enable the CSR checking. */
|
||||
};
|
||||
|
||||
@ -195,7 +183,7 @@ static struct riscv_set_options riscv_opts =
|
||||
0, /* rve */
|
||||
1, /* relax */
|
||||
DEFAULT_RISCV_ATTR, /* arch_attr */
|
||||
0. /* csr_check */
|
||||
0, /* csr_check */
|
||||
};
|
||||
|
||||
static void
|
||||
@ -337,7 +325,7 @@ riscv_set_arch (const char *s)
|
||||
riscv_parse_subset (&rps, s);
|
||||
}
|
||||
|
||||
/* Indicate -mabi= option is explictly set. */
|
||||
/* Indicate -mabi option is explictly set. */
|
||||
static bfd_boolean explicit_mabi = FALSE;
|
||||
|
||||
static void
|
||||
@ -348,9 +336,8 @@ riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
|
||||
rve_abi = rve;
|
||||
}
|
||||
|
||||
/* If the -mabi option isn't set, then we set the abi according to the arch
|
||||
string. Otherwise, check if there are conflicts between architecture
|
||||
and abi setting. */
|
||||
/* If the -mabi option isn't set, then set the abi according to the
|
||||
ISA string. Otherwise, check if there is any conflict. */
|
||||
|
||||
static void
|
||||
riscv_set_abi_by_arch (void)
|
||||
@ -388,27 +375,28 @@ static htab_t op_hash = NULL;
|
||||
static htab_t insn_type_hash = NULL;
|
||||
|
||||
/* This array holds the chars that always start a comment. If the
|
||||
pre-processor is disabled, these aren't very useful */
|
||||
pre-processor is disabled, these aren't very useful. */
|
||||
const char comment_chars[] = "#";
|
||||
|
||||
/* This array holds the chars that only start a comment at the beginning of
|
||||
a line. If the line seems to have the form '# 123 filename'
|
||||
.line and .file directives will appear in the pre-processed output */
|
||||
/* Note that input_file.c hand checks for '#' at the beginning of the
|
||||
.line and .file directives will appear in the pre-processed output
|
||||
|
||||
Note that input_file.c hand checks for '#' at the beginning of the
|
||||
first line of the input file. This is because the compiler outputs
|
||||
#NO_APP at the beginning of its output. */
|
||||
/* Also note that C style comments are always supported. */
|
||||
#NO_APP at the beginning of its output.
|
||||
|
||||
Also note that C style comments are always supported. */
|
||||
const char line_comment_chars[] = "#";
|
||||
|
||||
/* This array holds machine specific line separator characters. */
|
||||
const char line_separator_chars[] = ";";
|
||||
|
||||
/* Chars that can be used to separate mant from exp in floating point nums */
|
||||
/* Chars that can be used to separate mant from exp in floating point nums. */
|
||||
const char EXP_CHARS[] = "eE";
|
||||
|
||||
/* Chars that mean this number is a floating point constant */
|
||||
/* As in 0f12.456 */
|
||||
/* or 0d1.2345e12 */
|
||||
/* Chars that mean this number is a floating point constant.
|
||||
As in 0f12.456 or 0d1.2345e12. */
|
||||
const char FLT_CHARS[] = "rRsSfFdDxXpP";
|
||||
|
||||
/* Indicate we are already assemble any instructions or not. */
|
||||
@ -626,6 +614,7 @@ static const struct opcode_name_t opcode_name_list[] =
|
||||
static htab_t opcode_names_hash = NULL;
|
||||
|
||||
/* Initialization for hash table of opcode name. */
|
||||
|
||||
static void
|
||||
init_opcode_names_hash (void)
|
||||
{
|
||||
@ -636,8 +625,9 @@ init_opcode_names_hash (void)
|
||||
as_fatal (_("duplicate %s"), opcode->name);
|
||||
}
|
||||
|
||||
/* Find `s` is a valid opcode name or not,
|
||||
return the opcode name info if found. */
|
||||
/* Find `s` is a valid opcode name or not, return the opcode name info
|
||||
if found. */
|
||||
|
||||
static const struct opcode_name_t *
|
||||
opcode_name_lookup (char **s)
|
||||
{
|
||||
@ -703,6 +693,7 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
|
||||
}
|
||||
|
||||
/* Init hash table csr_extra_hash to handle CSR. */
|
||||
|
||||
static void
|
||||
riscv_init_csr_hash (const char *name,
|
||||
unsigned address,
|
||||
@ -726,7 +717,7 @@ riscv_init_csr_hash (const char *name,
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
/* Duplicate setting for the CSR, just return and do nothing. */
|
||||
/* Duplicate CSR. */
|
||||
if (!need_enrty)
|
||||
return;
|
||||
|
||||
@ -737,17 +728,21 @@ riscv_init_csr_hash (const char *name,
|
||||
entry->abort_version = abort_version;
|
||||
entry->next = NULL;
|
||||
|
||||
/* If the CSR hasn't been inserted in the hash table, then insert it.
|
||||
Otherwise, attach the extra information to the entry which is already
|
||||
in the hash table. */
|
||||
if (pre_entry == NULL)
|
||||
str_hash_insert (csr_extra_hash, name, entry, 0);
|
||||
else
|
||||
pre_entry->next = entry;
|
||||
}
|
||||
|
||||
/* Return the suitable CSR address after checking the ISA dependency and
|
||||
priv spec versions. */
|
||||
/* Return the CSR address after checking the ISA dependency and
|
||||
the privileged spec version.
|
||||
|
||||
There are one warning and two errors for CSR,
|
||||
|
||||
Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
|
||||
or the privileged spec, report warning only if -mcsr-check is set.
|
||||
Unknown CSR: the CSR has never been defined, report error.
|
||||
Improper CSR: the CSR number over the range (> 0xfff), report error. */
|
||||
|
||||
static unsigned int
|
||||
riscv_csr_address (const char *csr_name,
|
||||
@ -777,7 +772,6 @@ riscv_csr_address (const char *csr_name,
|
||||
as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
|
||||
}
|
||||
|
||||
/* Don't report the ISA conflict when -mcsr-check isn't set. */
|
||||
if (riscv_opts.csr_check && !result)
|
||||
as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
|
||||
|
||||
@ -787,16 +781,14 @@ riscv_csr_address (const char *csr_name,
|
||||
|| (default_priv_spec >= entry->define_version
|
||||
&& default_priv_spec < entry->abort_version))
|
||||
{
|
||||
/* Find the suitable CSR according to the specific version. */
|
||||
/* Find the CSR according to the specific version. */
|
||||
return entry->address;
|
||||
}
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
/* We can not find the suitable CSR address according to the privilege
|
||||
version. Therefore, we use the last defined value. Report the warning
|
||||
only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
|
||||
otherwise, you may get the unexpected CSR address. */
|
||||
/* Can not find the CSR address from the chosen privileged version,
|
||||
so use the newly defined value. */
|
||||
if (riscv_opts.csr_check)
|
||||
{
|
||||
const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
|
||||
@ -809,10 +801,8 @@ riscv_csr_address (const char *csr_name,
|
||||
return saved_entry->address;
|
||||
}
|
||||
|
||||
/* Once the CSR is defined, including the old privilege spec, then we call
|
||||
riscv_csr_class_check and riscv_csr_version_check to do the further checking
|
||||
and get the corresponding address. Return -1 if the CSR is never been
|
||||
defined. Otherwise, return the address. */
|
||||
/* Return -1 if the CSR has never been defined. Otherwise, return
|
||||
the address. */
|
||||
|
||||
static unsigned int
|
||||
reg_csr_lookup_internal (const char *s)
|
||||
@ -823,12 +813,6 @@ reg_csr_lookup_internal (const char *s)
|
||||
if (r == NULL)
|
||||
return -1U;
|
||||
|
||||
/* We just report the warning when the CSR is invalid. "Invalid CSR" means
|
||||
the CSR was defined, but isn't allowed for the current ISA setting or
|
||||
the privilege spec. If the CSR is never been defined, then assembler
|
||||
will regard it as a "Unknown CSR" and report error. If user use number
|
||||
to set the CSR, but over the range (> 0xfff), then assembler will report
|
||||
"Improper CSR" error for it. */
|
||||
return riscv_csr_address (s, r);
|
||||
}
|
||||
|
||||
@ -900,9 +884,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
|
||||
|
||||
/* For consistency checking, verify that all bits are specified either
|
||||
by the match/mask part of the instruction definition, or by the
|
||||
operand list.
|
||||
operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
|
||||
|
||||
`length` could be 0, 4 or 8, 0 for auto detection. */
|
||||
static bfd_boolean
|
||||
validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
{
|
||||
@ -934,7 +917,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
switch (c = *p++)
|
||||
{
|
||||
case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
|
||||
case 'c': break; /* RS1, constrained to equal sp */
|
||||
case 'c': break; /* RS1, constrained to equal sp. */
|
||||
case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
|
||||
case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
@ -947,14 +930,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
|
||||
case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
case 'w': break; /* RS1S, constrained to equal RD */
|
||||
case 'x': break; /* RS2S, constrained to equal RD */
|
||||
case 'z': break; /* RS2S, contrained to be x0 */
|
||||
case 'w': break; /* RS1S, constrained to equal RD. */
|
||||
case 'x': break; /* RS2S, constrained to equal RD. */
|
||||
case 'z': break; /* RS2S, constrained to be x0. */
|
||||
case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
|
||||
case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
|
||||
case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
|
||||
case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
|
||||
case 'U': break; /* RS1, constrained to equal RD */
|
||||
case 'U': break; /* RS1, constrained to equal RD. */
|
||||
case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
|
||||
case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
||||
@ -962,7 +945,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
|
||||
case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
|
||||
case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
|
||||
case 'F': /* funct */
|
||||
case 'F': /* RVC funct for .insn directive. */
|
||||
switch (c = *p++)
|
||||
{
|
||||
case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
|
||||
@ -994,7 +977,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
case 'I': break;
|
||||
case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
|
||||
case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
|
||||
case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
|
||||
case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1);
|
||||
/* Fall through. */
|
||||
case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
|
||||
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
||||
case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
|
||||
@ -1014,7 +998,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
case ']': break;
|
||||
case '0': break;
|
||||
case '1': break;
|
||||
case 'F': /* funct */
|
||||
case 'F': /* Funct for .insn directive. */
|
||||
switch (c = *p++)
|
||||
{
|
||||
case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
|
||||
@ -1027,7 +1011,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
|
||||
return FALSE;
|
||||
}
|
||||
break;
|
||||
case 'O': /* opcode */
|
||||
case 'O': /* Opcode for .insn directive. */
|
||||
switch (c = *p++)
|
||||
{
|
||||
case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
|
||||
@ -1062,8 +1046,9 @@ struct percent_op_match
|
||||
bfd_reloc_code_real_type reloc;
|
||||
};
|
||||
|
||||
/* Common hash table initialization function for
|
||||
instruction and .insn directive. */
|
||||
/* Common hash table initialization function for instruction and .insn
|
||||
directive. */
|
||||
|
||||
static htab_t
|
||||
init_opcode_hash (const struct riscv_opcode *opcodes,
|
||||
bfd_boolean insn_directive_p)
|
||||
@ -1224,9 +1209,9 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
|
||||
}
|
||||
|
||||
/* Build an instruction created by a macro expansion. This is passed
|
||||
a pointer to the count of instructions created so far, an
|
||||
expression, the name of the instruction to build, an operand format
|
||||
string, and corresponding arguments. */
|
||||
a pointer to the count of instructions created so far, an expression,
|
||||
the name of the instruction to build, an operand format string, and
|
||||
corresponding arguments. */
|
||||
|
||||
static void
|
||||
macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|
||||
@ -1316,6 +1301,7 @@ md_assemblef (const char *format, ...)
|
||||
|
||||
/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
|
||||
unset. */
|
||||
|
||||
static void
|
||||
normalize_constant_expr (expressionS *ex)
|
||||
{
|
||||
@ -1353,6 +1339,7 @@ make_internal_label (void)
|
||||
}
|
||||
|
||||
/* Load an entry from the GOT. */
|
||||
|
||||
static void
|
||||
pcrel_access (int destreg, int tempreg, expressionS *ep,
|
||||
const char *lo_insn, const char *lo_pattern,
|
||||
@ -1385,6 +1372,7 @@ pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
|
||||
}
|
||||
|
||||
/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
|
||||
|
||||
static void
|
||||
riscv_call (int destreg, int tempreg, expressionS *ep,
|
||||
bfd_reloc_code_real_type reloc)
|
||||
@ -1491,10 +1479,10 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
|
||||
if (imm_expr->X_op == O_constant)
|
||||
load_const (rd, imm_expr);
|
||||
else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
|
||||
else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
|
||||
pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
|
||||
BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
||||
else /* Local PIC symbol, or any non-PIC symbol */
|
||||
else /* Local PIC symbol, or any non-PIC symbol. */
|
||||
pcrel_load (rd, rd, imm_expr, "addi",
|
||||
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
||||
break;
|
||||
@ -1720,9 +1708,9 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
||||
}
|
||||
|
||||
/* Search for the start of the main expression.
|
||||
End the loop with CRUX pointing to the start
|
||||
of the main expression and with CRUX_DEPTH containing the number
|
||||
of open brackets at that point. */
|
||||
|
||||
End the loop with CRUX pointing to the start of the main expression and
|
||||
with CRUX_DEPTH containing the number of open brackets at that point. */
|
||||
reloc_index = -1;
|
||||
str_depth = 0;
|
||||
do
|
||||
@ -1758,6 +1746,7 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
||||
}
|
||||
|
||||
/* Parse opcode name, could be an mnemonics or number. */
|
||||
|
||||
static size_t
|
||||
my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
||||
char *str, const struct percent_op_match *percent_op)
|
||||
@ -1794,7 +1783,6 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
|
||||
}
|
||||
|
||||
/* All RISC-V CSR instructions belong to one of these classes. */
|
||||
|
||||
enum csr_insn_type
|
||||
{
|
||||
INSN_NOT_CSR,
|
||||
@ -1864,11 +1852,7 @@ riscv_is_priv_insn (insn_t insn)
|
||||
|| ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
|
||||
|| ((insn ^ MATCH_WFI) & MASK_WFI) == 0
|
||||
/* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
|
||||
check it here to keep the compatible. Maybe we should issue warning
|
||||
if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
|
||||
We already have a similar check for CSR, but not yet for instructions.
|
||||
It would be good if we could check the spec versions both for CSR and
|
||||
instructions, but not here. */
|
||||
check it here to keep the compatible. */
|
||||
|| ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
|
||||
}
|
||||
|
||||
@ -1966,7 +1950,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
case 'C': /* RVC */
|
||||
switch (*++args)
|
||||
{
|
||||
case 's': /* RS1 x8-x15 */
|
||||
case 's': /* RS1 x8-x15. */
|
||||
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
||||
|| !(regno >= 8 && regno <= 15))
|
||||
break;
|
||||
@ -1977,7 +1961,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
|| EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
|
||||
break;
|
||||
continue;
|
||||
case 't': /* RS2 x8-x15 */
|
||||
case 't': /* RS2 x8-x15. */
|
||||
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
||||
|| !(regno >= 8 && regno <= 15))
|
||||
break;
|
||||
@ -2003,7 +1987,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
|| regno != X_SP)
|
||||
break;
|
||||
continue;
|
||||
case 'z': /* RS2, contrained to equal x0. */
|
||||
case 'z': /* RS2, constrained to equal x0. */
|
||||
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
||||
|| regno != 0)
|
||||
break;
|
||||
@ -2346,7 +2330,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
case 'd': /* Destination register. */
|
||||
case 's': /* Source register. */
|
||||
case 't': /* Target register. */
|
||||
case 'r': /* rs3. */
|
||||
case 'r': /* RS3 */
|
||||
if (reg_lookup (&s, RCLASS_GPR, ®no))
|
||||
{
|
||||
c = *args;
|
||||
@ -2374,11 +2358,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
}
|
||||
break;
|
||||
|
||||
case 'D': /* Floating point rd. */
|
||||
case 'S': /* Floating point rs1. */
|
||||
case 'T': /* Floating point rs2. */
|
||||
case 'U': /* Floating point rs1 and rs2. */
|
||||
case 'R': /* Floating point rs3. */
|
||||
case 'D': /* Floating point RD. */
|
||||
case 'S': /* Floating point RS1. */
|
||||
case 'T': /* Floating point RS2. */
|
||||
case 'U': /* Floating point RS1 and RS2. */
|
||||
case 'R': /* Floating point RS3. */
|
||||
if (reg_lookup (&s, RCLASS_FPR, ®no))
|
||||
{
|
||||
c = *args;
|
||||
@ -2394,7 +2378,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
break;
|
||||
case 'U':
|
||||
INSERT_OPERAND (RS1, *ip, regno);
|
||||
/* fallthru */
|
||||
/* Fall through. */
|
||||
case 'T':
|
||||
INSERT_OPERAND (RS2, *ip, regno);
|
||||
break;
|
||||
@ -2449,10 +2433,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
||||
p = percent_op_itype;
|
||||
*imm_reloc = BFD_RELOC_RISCV_LO12_I;
|
||||
goto load_store;
|
||||
case '1': /* 4-operand add, must be %tprel_add. */
|
||||
case '1':
|
||||
/* This is used for TLS, where the fourth operand is
|
||||
%tprel_add, to get a relocation applied to an add
|
||||
instruction, for relaxation to use. */
|
||||
p = percent_op_rtype;
|
||||
goto alu_op;
|
||||
case '0': /* AMO "displacement," which must be zero. */
|
||||
case '0': /* AMO displacement, which must be zero. */
|
||||
p = percent_op_null;
|
||||
load_store:
|
||||
if (riscv_handle_implicit_zero_offset (imm_expr, s))
|
||||
@ -2645,13 +2632,13 @@ md_assemble (char *str)
|
||||
expressionS imm_expr;
|
||||
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
|
||||
|
||||
/* The arch and priv attributes should be set before assembling. */
|
||||
/* The architecture and privileged elf attributes should be set
|
||||
before assembling. */
|
||||
if (!start_assemble)
|
||||
{
|
||||
start_assemble = TRUE;
|
||||
riscv_set_abi_by_arch ();
|
||||
|
||||
/* Set the default_priv_spec according to the priv attributes. */
|
||||
riscv_set_abi_by_arch ();
|
||||
if (!riscv_set_default_priv_spec (NULL))
|
||||
return;
|
||||
}
|
||||
@ -2734,8 +2721,6 @@ md_parse_option (int c, const char *arg)
|
||||
switch (c)
|
||||
{
|
||||
case OPTION_MARCH:
|
||||
/* riscv_after_parse_args will call riscv_set_arch to parse
|
||||
the architecture. */
|
||||
default_arch_with_ext = arg;
|
||||
break;
|
||||
|
||||
@ -2819,10 +2804,8 @@ md_parse_option (int c, const char *arg)
|
||||
void
|
||||
riscv_after_parse_args (void)
|
||||
{
|
||||
/* The --with-arch is optional for now, so we have to set the xlen
|
||||
according to the default_arch, which is set by the --targte, first.
|
||||
Then, we use the xlen to set the default_arch_with_ext if the
|
||||
-march and --with-arch are not set. */
|
||||
/* The --with-arch is optional for now, so we still need to set the xlen
|
||||
according to the default_arch, which is set by the --target. */
|
||||
if (xlen == 0)
|
||||
{
|
||||
if (strcmp (default_arch, "riscv32") == 0)
|
||||
@ -2838,12 +2821,12 @@ riscv_after_parse_args (void)
|
||||
/* Initialize the hash table for extensions with default version. */
|
||||
ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
|
||||
|
||||
/* If the -misa-spec isn't set, then we set the default ISA spec according
|
||||
to DEFAULT_RISCV_ISA_SPEC. */
|
||||
/* Set default specs. */
|
||||
if (default_isa_spec == ISA_SPEC_CLASS_NONE)
|
||||
riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
|
||||
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
|
||||
riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
|
||||
|
||||
/* Set the architecture according to -march or or --with-arch. */
|
||||
riscv_set_arch (default_arch_with_ext);
|
||||
|
||||
/* Add the RVC extension, regardless of -march, to support .option rvc. */
|
||||
@ -2856,11 +2839,6 @@ riscv_after_parse_args (void)
|
||||
if (riscv_subset_supports ("e"))
|
||||
riscv_set_rve (TRUE);
|
||||
|
||||
/* If the -mpriv-spec isn't set, then we set the default privilege spec
|
||||
according to DEFAULT_PRIV_SPEC. */
|
||||
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
|
||||
riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
|
||||
|
||||
/* If the CIE to be produced has not been overridden on the command line,
|
||||
then produce version 3 by default. This allows us to use the full
|
||||
range of registers in a .cfi_return_column directive. */
|
||||
@ -3167,9 +3145,7 @@ riscv_pre_output_hook (void)
|
||||
subseg_set (seg, subseg);
|
||||
}
|
||||
|
||||
|
||||
/* This structure is used to hold a stack of .option values. */
|
||||
|
||||
struct riscv_option_stack
|
||||
{
|
||||
struct riscv_option_stack *next;
|
||||
@ -3563,6 +3539,7 @@ RISC-V options:\n\
|
||||
}
|
||||
|
||||
/* Standard calling conventions leave the CFA at SP on entry. */
|
||||
|
||||
void
|
||||
riscv_cfi_frame_initial_instructions (void)
|
||||
{
|
||||
@ -3647,41 +3624,37 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
|
||||
demand_empty_rest_of_line ();
|
||||
}
|
||||
|
||||
/* Update arch and priv attributes. If we don't set the corresponding ELF
|
||||
attributes, then try to output the default ones. */
|
||||
/* Update architecture and privileged elf attributes. If we don't set
|
||||
them, then try to output the default ones. */
|
||||
|
||||
static void
|
||||
riscv_write_out_attrs (void)
|
||||
{
|
||||
const char *arch_str, *priv_str, *p;
|
||||
/* versions[0] is major, versions[1] is minor,
|
||||
and versions[3] is revision. */
|
||||
/* versions[0]: major version.
|
||||
versions[1]: minor version.
|
||||
versions[2]: revision version. */
|
||||
unsigned versions[3] = {0}, number = 0;
|
||||
unsigned int i;
|
||||
|
||||
/* Re-write arch attribute to normalize the arch string. */
|
||||
/* Re-write architecture elf attribute. */
|
||||
arch_str = riscv_arch_str (xlen, &riscv_subsets);
|
||||
bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
|
||||
xfree ((void *)arch_str);
|
||||
|
||||
/* For the file without any instruction, we don't set the default_priv_spec
|
||||
according to the priv attributes since the md_assemble isn't called.
|
||||
Call riscv_set_default_priv_spec here for the above case, although
|
||||
it seems strange. */
|
||||
according to the privileged elf attributes since the md_assemble isn't
|
||||
called. */
|
||||
if (!start_assemble
|
||||
&& !riscv_set_default_priv_spec (NULL))
|
||||
return;
|
||||
|
||||
/* If we already have set elf priv attributes, then no need to do anything,
|
||||
assembler will generate them according to what you set. Otherwise, don't
|
||||
generate or update them when no CSR and priv instructions are used.
|
||||
Generate the priv attributes according to default_priv_spec, which can be
|
||||
set by -mpriv-spec and --with-priv-spec, and be updated by the original
|
||||
priv attribute sets. */
|
||||
/* If we already have set privileged elf attributes, then no need to do
|
||||
anything. Otherwise, don't generate or update them when no CSR and
|
||||
privileged instructions are used. */
|
||||
if (!explicit_priv_attr)
|
||||
return;
|
||||
|
||||
/* Re-write priv attributes by default_priv_spec. */
|
||||
priv_str = riscv_get_priv_spec_name (default_priv_spec);
|
||||
p = priv_str;
|
||||
for (i = 0; *p; ++p)
|
||||
@ -3701,15 +3674,13 @@ riscv_write_out_attrs (void)
|
||||
}
|
||||
versions[i] = number;
|
||||
|
||||
/* Set the priv attributes. */
|
||||
/* Re-write privileged elf attributes. */
|
||||
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
|
||||
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
|
||||
bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
|
||||
}
|
||||
|
||||
/* Add the default contents for the .riscv.attributes section. If any
|
||||
ELF attribute or -march-attr options is set, call riscv_write_out_attrs
|
||||
to update the arch and priv attributes. */
|
||||
/* Add the default contents for the .riscv.attributes section. */
|
||||
|
||||
static void
|
||||
riscv_set_public_attributes (void)
|
||||
@ -3806,11 +3777,9 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
|
||||
}
|
||||
}
|
||||
|
||||
/* Pseudo-op table. */
|
||||
|
||||
/* RISC-V pseudo-ops table. */
|
||||
static const pseudo_typeS riscv_pseudo_table[] =
|
||||
{
|
||||
/* RISC-V-specific pseudo-ops. */
|
||||
{"option", s_riscv_option, 0},
|
||||
{"half", cons, 2},
|
||||
{"word", cons, 4},
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
|
||||
|
||||
* elf/riscv.h: Comments tidy and improvement.
|
||||
* opcode/riscv-opc.h: Likewise.
|
||||
* opcode/riscv.h: Likewise.
|
||||
|
||||
2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
||||
|
||||
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete.
|
||||
|
||||
@ -121,7 +121,6 @@ END_RELOC_NUMBERS (R_RISCV_max)
|
||||
#define SHT_RISCV_ATTRIBUTES 0x70000003 /* Section holds attributes. */
|
||||
|
||||
/* Object attributes. */
|
||||
|
||||
enum
|
||||
{
|
||||
/* 0-3 are generic. */
|
||||
|
||||
@ -669,7 +669,7 @@
|
||||
#define MASK_CUSTOM3_RD_RS1 0x707f
|
||||
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
|
||||
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
|
||||
/* Privileged CSR addresses (v1.11). */
|
||||
/* Privileged CSR addresses. */
|
||||
#define CSR_USTATUS 0x0
|
||||
#define CSR_UIE 0x4
|
||||
#define CSR_UTVEC 0x5
|
||||
@ -916,7 +916,7 @@
|
||||
#define CSR_TCONTROL 0x7a5
|
||||
#define CSR_MCONTEXT 0x7a8
|
||||
#define CSR_SCONTEXT 0x7aa
|
||||
#endif /* RISCV_ENCODING_H. */
|
||||
#endif /* RISCV_ENCODING_H */
|
||||
#ifdef DECLARE_INSN
|
||||
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
|
||||
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
|
||||
@ -1238,9 +1238,9 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
|
||||
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
|
||||
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
|
||||
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
|
||||
#endif /* DECLARE_INSN. */
|
||||
#endif /* DECLARE_INSN */
|
||||
#ifdef DECLARE_CSR
|
||||
/* Privileged. */
|
||||
/* Privileged CSRs. */
|
||||
DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
@ -1453,7 +1453,7 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
|
||||
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
|
||||
/* Dropped. */
|
||||
/* Dropped CSRs. */
|
||||
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
@ -1472,7 +1472,7 @@ DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CL
|
||||
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
/* Unprivileged. */
|
||||
/* Unprivileged CSRs. */
|
||||
DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
@ -1488,7 +1488,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
|
||||
DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
#endif /* DECLARE_CSR. */
|
||||
#endif /* DECLARE_CSR */
|
||||
#ifdef DECLARE_CSR_ALIAS
|
||||
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
|
||||
@ -1502,4 +1502,4 @@ DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
|
||||
DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
||||
#endif /* DECLARE_CSR_ALIAS. */
|
||||
#endif /* DECLARE_CSR_ALIAS */
|
||||
|
||||
@ -29,13 +29,13 @@ typedef uint64_t insn_t;
|
||||
|
||||
static inline unsigned int riscv_insn_length (insn_t insn)
|
||||
{
|
||||
if ((insn & 0x3) != 0x3) /* RVC. */
|
||||
if ((insn & 0x3) != 0x3) /* RVC instructions. */
|
||||
return 2;
|
||||
if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
|
||||
if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
|
||||
return 4;
|
||||
if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */
|
||||
if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
|
||||
return 6;
|
||||
if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */
|
||||
if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
|
||||
return 8;
|
||||
/* Longer instructions not supported at the moment. */
|
||||
return 2;
|
||||
@ -295,7 +295,6 @@ static const char * const riscv_pred_succ[16] =
|
||||
#define MAX_SUBSET_NUM 4
|
||||
|
||||
/* All RISC-V instructions belong to at least one of these classes. */
|
||||
|
||||
enum riscv_insn_class
|
||||
{
|
||||
INSN_CLASS_NONE,
|
||||
@ -319,7 +318,6 @@ enum riscv_insn_class
|
||||
};
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
struct riscv_opcode
|
||||
{
|
||||
/* The name of the instruction. */
|
||||
@ -351,7 +349,6 @@ struct riscv_opcode
|
||||
};
|
||||
|
||||
/* The current supported ISA spec versions. */
|
||||
|
||||
enum riscv_isa_spec_class
|
||||
{
|
||||
ISA_SPEC_CLASS_NONE,
|
||||
@ -365,7 +362,6 @@ enum riscv_isa_spec_class
|
||||
#define RISCV_UNKNOWN_VERSION -1
|
||||
|
||||
/* This structure holds version information for specific ISA. */
|
||||
|
||||
struct riscv_ext_version
|
||||
{
|
||||
const char *name;
|
||||
@ -375,19 +371,17 @@ struct riscv_ext_version
|
||||
};
|
||||
|
||||
/* All RISC-V CSR belong to one of these classes. */
|
||||
|
||||
enum riscv_csr_class
|
||||
{
|
||||
CSR_CLASS_NONE,
|
||||
|
||||
CSR_CLASS_I,
|
||||
CSR_CLASS_I_32, /* rv32 only */
|
||||
CSR_CLASS_F, /* f-ext only */
|
||||
CSR_CLASS_DEBUG /* debug CSR */
|
||||
CSR_CLASS_I_32, /* RV32 only. */
|
||||
CSR_CLASS_F, /* F extension only. */
|
||||
CSR_CLASS_DEBUG /* Debug CSR. */
|
||||
};
|
||||
|
||||
/* The current supported privilege spec versions. */
|
||||
|
||||
enum riscv_priv_spec_class
|
||||
{
|
||||
PRIV_SPEC_CLASS_NONE,
|
||||
@ -399,7 +393,6 @@ enum riscv_priv_spec_class
|
||||
};
|
||||
|
||||
/* This structure holds all restricted conditions for a CSR. */
|
||||
|
||||
struct riscv_csr_extra
|
||||
{
|
||||
/* Class to which this CSR belongs. Used to decide whether or
|
||||
@ -452,14 +445,7 @@ struct riscv_csr_extra
|
||||
disassembler, and requires special treatment by the assembler. */
|
||||
#define INSN_MACRO 0xffffffff
|
||||
|
||||
/* This is a list of macro expanded instructions.
|
||||
|
||||
_I appended means immediate
|
||||
_A appended means address
|
||||
_AB appended means address with base register
|
||||
_D appended means 64 bit floating point constant
|
||||
_S appended means 32 bit floating point constant. */
|
||||
|
||||
/* This is a list of macro expanded instructions. */
|
||||
enum
|
||||
{
|
||||
M_LA,
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
|
||||
|
||||
* riscv-dis.c: Comments tidy and improvement.
|
||||
* riscv-opc.c: Likewise.
|
||||
|
||||
2021-01-13 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* Makefile.in: Regenerate.
|
||||
|
||||
@ -44,8 +44,8 @@ struct riscv_private_data
|
||||
static const char * const *riscv_gpr_names;
|
||||
static const char * const *riscv_fpr_names;
|
||||
|
||||
/* Other options. */
|
||||
static int no_aliases; /* If set disassemble as most general inst. */
|
||||
/* If set, disassemble as most general instruction. */
|
||||
static int no_aliases;
|
||||
|
||||
static void
|
||||
set_default_riscv_dis_options (void)
|
||||
@ -179,20 +179,20 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
||||
case 'C': /* RVC */
|
||||
switch (*++d)
|
||||
{
|
||||
case 's': /* RS1 x8-x15 */
|
||||
case 'w': /* RS1 x8-x15 */
|
||||
case 's': /* RS1 x8-x15. */
|
||||
case 'w': /* RS1 x8-x15. */
|
||||
print (info->stream, "%s",
|
||||
riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
|
||||
break;
|
||||
case 't': /* RS2 x8-x15 */
|
||||
case 'x': /* RS2 x8-x15 */
|
||||
case 't': /* RS2 x8-x15. */
|
||||
case 'x': /* RS2 x8-x15. */
|
||||
print (info->stream, "%s",
|
||||
riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
|
||||
break;
|
||||
case 'U': /* RS1, constrained to equal RD */
|
||||
case 'U': /* RS1, constrained to equal RD. */
|
||||
print (info->stream, "%s", riscv_gpr_names[rd]);
|
||||
break;
|
||||
case 'c': /* RS1, constrained to equal sp */
|
||||
case 'c': /* RS1, constrained to equal sp. */
|
||||
print (info->stream, "%s", riscv_gpr_names[X_SP]);
|
||||
break;
|
||||
case 'V': /* RS2 */
|
||||
@ -248,11 +248,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
||||
case '<':
|
||||
print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
|
||||
break;
|
||||
case 'T': /* floating-point RS2 */
|
||||
case 'T': /* Floating-point RS2. */
|
||||
print (info->stream, "%s",
|
||||
riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
|
||||
break;
|
||||
case 'D': /* floating-point RS2 x8-x15 */
|
||||
case 'D': /* Floating-point RS2 x8-x15. */
|
||||
print (info->stream, "%s",
|
||||
riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
|
||||
break;
|
||||
@ -268,7 +268,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
||||
break;
|
||||
|
||||
case '0':
|
||||
/* Only print constant 0 if it is the last argument */
|
||||
/* Only print constant 0 if it is the last argument. */
|
||||
if (!d[1])
|
||||
print (info->stream, "0");
|
||||
break;
|
||||
@ -371,7 +371,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
||||
|
||||
case 'E':
|
||||
{
|
||||
static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR. */
|
||||
static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */
|
||||
static bfd_boolean init_csr = FALSE;
|
||||
unsigned int csr = EXTRACT_OPERAND (CSR, l);
|
||||
|
||||
@ -381,7 +381,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
||||
for (i = 0; i < 4096; i++)
|
||||
riscv_csr_hash[i] = NULL;
|
||||
|
||||
/* Set to the newest privilege version. */
|
||||
/* Set to the newest privileged version. */
|
||||
if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
|
||||
default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
|
||||
|
||||
@ -593,8 +593,6 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
|
||||
disassembler_ftype
|
||||
riscv_get_disassembler (bfd *abfd)
|
||||
{
|
||||
/* If -Mpriv-spec= isn't set, then try to set it by checking the elf
|
||||
privileged attributes. */
|
||||
if (abfd)
|
||||
{
|
||||
const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
|
||||
|
||||
@ -280,8 +280,6 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
|
||||
{"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
|
||||
{"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
|
||||
/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
|
||||
applied to an add instruction, for relaxation to use. */
|
||||
{"add", 0, INSN_CLASS_I, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 },
|
||||
{"add", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
|
||||
{"la", 0, INSN_CLASS_I, "d,B", 0, (int) M_LA, match_never, INSN_MACRO },
|
||||
@ -395,7 +393,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"subw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
|
||||
{"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
|
||||
|
||||
/* Atomic memory operation instruction subset */
|
||||
/* Atomic memory operation instruction subset. */
|
||||
{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
@ -485,7 +483,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"amomin.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
|
||||
{"amominu.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
|
||||
|
||||
/* Multiply/Divide instruction subset */
|
||||
/* Multiply/Divide instruction subset. */
|
||||
{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
|
||||
{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
|
||||
{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
|
||||
@ -500,7 +498,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
|
||||
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
|
||||
|
||||
/* Bitmanip instruction subset - ZBA/ZBB/ZBC */
|
||||
/* Bitmanip instruction subset - ZBA/ZBB/ZBC. */
|
||||
{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
|
||||
{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
|
||||
{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
|
||||
@ -548,7 +546,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
|
||||
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
|
||||
|
||||
/* Single-precision floating-point instruction subset */
|
||||
/* Single-precision floating-point instruction subset. */
|
||||
{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
{"fscsr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
|
||||
@ -629,7 +627,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"fcvt.s.lu", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.s.lu", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
|
||||
|
||||
/* Double-precision floating-point instruction subset */
|
||||
/* Double-precision floating-point instruction subset. */
|
||||
{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
|
||||
{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
|
||||
{"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
|
||||
@ -690,7 +688,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
|
||||
|
||||
/* Quad-precision floating-point instruction subset */
|
||||
/* Quad-precision floating-point instruction subset. */
|
||||
{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
|
||||
{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
|
||||
{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
|
||||
@ -799,7 +797,7 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
|
||||
|
||||
/* Supervisor instructions */
|
||||
/* Supervisor instructions. */
|
||||
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },
|
||||
{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
|
||||
{"csrsi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
|
||||
@ -932,6 +930,7 @@ const struct riscv_opcode riscv_insn_types[] =
|
||||
{"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 },
|
||||
|
||||
{"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 },
|
||||
|
||||
/* Terminate the list. */
|
||||
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
||||
};
|
||||
@ -939,7 +938,7 @@ const struct riscv_opcode riscv_insn_types[] =
|
||||
/* All standard extensions defined in all supported ISA spec. */
|
||||
const struct riscv_ext_version riscv_ext_version_table[] =
|
||||
{
|
||||
/* name, ISA spec, major version, minor_version. */
|
||||
/* name, ISA spec, major version, minor version. */
|
||||
{"e", ISA_SPEC_CLASS_20191213, 1, 9},
|
||||
{"e", ISA_SPEC_CLASS_20190608, 1, 9},
|
||||
{"e", ISA_SPEC_CLASS_2P2, 1, 9},
|
||||
|
||||
Reference in New Issue
Block a user