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* simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
This commit is contained in:
Jeff Law
@ -1,5 +1,7 @@
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Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
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* interp.c (do_format_5): Get operands correctly and
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* interp.c (do_format_5): Get operands correctly and
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call the target function.
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call the target function.
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(sim_resume): Don't do a PC update for format 5 instructions.
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(sim_resume): Don't do a PC update for format 5 instructions.
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@ -2,11 +2,6 @@
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#include "v850_sim.h"
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#include "v850_sim.h"
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#include "simops.h"
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#include "simops.h"
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void
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OP_220 ()
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{
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}
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void
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void
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OP_10760 ()
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OP_10760 ()
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{
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{
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@ -637,6 +632,177 @@ OP_7E0 ()
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State.regs[OP[1]] = result;
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State.regs[OP[1]] = result;
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}
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}
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/* satadd reg,reg */
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void
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OP_C0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov, sat;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
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| (sat ? PSW_SAT : 0));
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/* Handle saturated results. */
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if (sat && (op0 & 0x80000000))
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State.regs[OP[1]] = 0x80000000;
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else if (sat)
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State.regs[OP[1]] = 0x7fffffff;
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}
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/* satadd sign_extend(imm5), reg */
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void
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OP_220 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov, sat;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0x1f);
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temp = (temp << 27) >> 27;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
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| (sat ? PSW_SAT : 0));
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/* Handle saturated results. */
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if (sat && (op0 & 0x80000000))
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State.regs[OP[1]] = 0x80000000;
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else if (sat)
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State.regs[OP[1]] = 0x7fffffff;
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}
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/* satsub reg1, reg2 */
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void
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OP_A0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov, sat;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
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| (sat ? PSW_SAT : 0));
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/* Handle saturated results. */
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if (sat && (op1 & 0x80000000))
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State.regs[OP[1]] = 0x80000000;
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else if (sat)
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State.regs[OP[1]] = 0x7fffffff;
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}
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/* satsubi sign_extend(imm16), reg */
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void
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OP_660 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov, sat;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0xffff);
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temp = (temp << 16) >> 16;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
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| (sat ? PSW_SAT : 0));
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/* Handle saturated results. */
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if (sat && (op1 & 0x80000000))
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State.regs[OP[1]] = 0x80000000;
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else if (sat)
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State.regs[OP[1]] = 0x7fffffff;
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}
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void
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OP_80 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov, sat;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 - op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < -op0);
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ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
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&& (op1 & 0x80000000) != (result & 0x80000000));
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sat = ov;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
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| (sat ? PSW_SAT : 0));
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/* Handle saturated results. */
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if (sat && (op0 & 0x80000000))
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State.regs[OP[1]] = 0x80000000;
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else if (sat)
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State.regs[OP[1]] = 0x7fffffff;
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}
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/* tst reg,reg */
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/* tst reg,reg */
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void
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void
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OP_160 ()
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OP_160 ()
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@ -727,21 +893,11 @@ OP_1687E0 ()
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{
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{
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}
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}
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void
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OP_A0 ()
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{
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}
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void
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void
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OP_740 ()
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OP_740 ()
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{
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{
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}
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}
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void
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OP_80 ()
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{
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}
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/* sar zero_extend(imm5),reg1 */
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/* sar zero_extend(imm5),reg1 */
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void
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void
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OP_2A0 ()
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OP_2A0 ()
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@ -1026,11 +1182,6 @@ OP_20 ()
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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}
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}
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void
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OP_C0 ()
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{
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}
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void
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void
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OP_480 ()
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OP_480 ()
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{
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{
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@ -1105,8 +1256,3 @@ OP_700 ()
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{
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{
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}
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}
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void
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OP_660 ()
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{
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}
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