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[ARC] Update instruction type and delay slot info.

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This patch corrects the instructioninformation passed into the
disassebler_info structure.

include/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_subclass_t): Add COND.
	(flag_class_t): Add F_CLASS_EXTEND.

opcodes/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
	information.
	(print_insn_arc): Set insn_type information.
	* arc-opc.c (C_CC): Add F_CLASS_COND.
	* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
	(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
	(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
	(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
	(brne, brne_s, jeq_s, jne_s): Likewise.
This commit is contained in:
Claudiu Zissulescu
2016-05-19 12:19:32 +02:00
parent 87789e08e5
commit d9eca1df01
6 changed files with 154 additions and 114 deletions
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6
include/opcode/arc.h
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@ -59,6 +59,7 @@ typedef enum
BTSCN,
CD1,
CD2,
COND,
DIV,
DP,
DPA,
@ -91,7 +92,10 @@ typedef enum
/* The conditional code can be extended over the standard variants
via .extCondCode pseudo-op. */
F_CLASS_EXTEND = (1 << 2)
F_CLASS_EXTEND = (1 << 2),
/* Condition code flag. */
F_CLASS_COND = (1 << 3)
} flag_class_t;
/* The opcode table is an array of struct arc_opcode. */