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gas/testsuite/

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2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
	* gas/i386/x86-64-sse-noavx.s: Likewise.

	* gas/i386/sse-noavx.d: Updated.
	* gas/i386/x86-64-sse-noavx.d: Likewise.

opcodes/

2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
2008-05-21 21:40:57 +00:00
parent 7d9e3d9854
commit d9479f2d8d
8 changed files with 25 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
gas/testsuite/ChangeLog
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@ -1,3 +1,11 @@
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
* gas/i386/x86-64-sse-noavx.s: Likewise.
* gas/i386/sse-noavx.d: Updated.
* gas/i386/x86-64-sse-noavx.d: Likewise.
2008-05-09 Catherine Moore <clm@codesourcery.com> 2008-05-09 Catherine Moore <clm@codesourcery.com>
* gas/mips/mips16-hilo-match.s: New test. * gas/mips/mips16-hilo-match.s: New test.

2
gas/testsuite/gas/i386/sse-noavx.d
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@ -15,7 +15,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\) [ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\)
[ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0
[ ]*[a-f0-9]+: 0f 01 c8 monitor %eax,%ecx,%edx [ ]*[a-f0-9]+: 0f 01 c8 monitor %eax,%ecx,%edx
[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1
[ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%eax\) [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%eax\)
[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1
[ ]*[a-f0-9]+: 0f 01 c9 mwait %eax,%ecx [ ]*[a-f0-9]+: 0f 01 c9 mwait %eax,%ecx
[ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0
[ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0

2
gas/testsuite/gas/i386/sse-noavx.s
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@ -10,7 +10,9 @@ _start:
fisttpll (%eax) fisttpll (%eax)
maskmovq %mm7,%mm0 maskmovq %mm7,%mm0
monitor monitor
movdq2q %xmm0, %mm1
movntq %mm2,(%eax) movntq %mm2,(%eax)
movq2dq %mm0, %xmm1
mwait mwait
pabsb %mm1,%mm0 pabsb %mm1,%mm0
pabsd %mm1,%mm0 pabsd %mm1,%mm0

2
gas/testsuite/gas/i386/x86-64-sse-noavx.d
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@ -16,7 +16,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\) [ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\)
[ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0
[ ]*[a-f0-9]+: 0f 01 c8 monitor %rax,%rcx,%rdx [ ]*[a-f0-9]+: 0f 01 c8 monitor %rax,%rcx,%rdx
[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1
[ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%rax\) [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%rax\)
[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1
[ ]*[a-f0-9]+: 0f 01 c9 mwait %rax,%rcx [ ]*[a-f0-9]+: 0f 01 c9 mwait %rax,%rcx
[ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0
[ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0

2
gas/testsuite/gas/i386/x86-64-sse-noavx.s
View File

@ -11,7 +11,9 @@ _start:
fisttpll (%rax) fisttpll (%rax)
maskmovq %mm7,%mm0 maskmovq %mm7,%mm0
monitor monitor
movdq2q %xmm0, %mm1
movntq %mm2,(%rax) movntq %mm2,(%rax)
movq2dq %mm0, %xmm1
mwait mwait
pabsb %mm1,%mm0 pabsb %mm1,%mm0
pabsd %mm1,%mm0 pabsd %mm1,%mm0

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
* i386-tbl.h: Regenerated.
2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
* cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond. * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.

4
opcodes/i386-opc.tbl
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@ -1453,8 +1453,8 @@ movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|N
movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMMX } movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegXMM } movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }

4
opcodes/i386-tbl.h
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@ -13206,7 +13206,7 @@ const template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1,
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } }, 0, 0, 0, 0, 0, 0 } },
@ -13218,7 +13218,7 @@ const template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1,
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } }, 0, 0, 0, 0, 0, 0 } },