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MIPS16: Reassign 0' and 4' operand codes

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Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range.  No functional change.

	gas/
	* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_macro): Likewise.

	include/
	* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
	`F' respectively.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_opcodes): Likewise.
This commit is contained in:
Maciej W. Rozycki
2016-12-23 17:05:01 +00:00
parent 0674ee5dad
commit d8722d7641
6 changed files with 43 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
2016-12-23 Maciej W. Rozycki <macro@imgtec.com> 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix

10
gas/config/tc-mips.c
View File

@ -8758,15 +8758,15 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
case ')': case ')':
break; break;
case '0': case '.':
case 'S': case 'S':
case 'P': case 'P':
case 'R': case 'R':
break; break;
case '<': case '<':
case '4':
case '5': case '5':
case 'F':
case 'H': case 'H':
case 'W': case 'W':
case 'D': case 'D':
@ -13531,7 +13531,7 @@ mips16_macro (struct mips_cl_insn *ip)
s = "mfhi"; s = "mfhi";
do_div3: do_div3:
start_noreorder (); start_noreorder ();
macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]); macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
expr1.X_add_number = 2; expr1.X_add_number = 2;
macro_build (&expr1, "bnez", "x,p", op[2]); macro_build (&expr1, "bnez", "x,p", op[2]);
macro_build (NULL, "break", "6", 7); macro_build (NULL, "break", "6", 7);
@ -13561,7 +13561,7 @@ mips16_macro (struct mips_cl_insn *ip)
s2 = "mfhi"; s2 = "mfhi";
do_divu3: do_divu3:
start_noreorder (); start_noreorder ();
macro_build (NULL, s, "0,x,y", op[1], op[2]); macro_build (NULL, s, ".,x,y", op[1], op[2]);
expr1.X_add_number = 2; expr1.X_add_number = 2;
macro_build (&expr1, "bnez", "x,p", op[2]); macro_build (&expr1, "bnez", "x,p", op[2]);
macro_build (NULL, "break", "6", 7); macro_build (NULL, "break", "6", 7);
@ -13583,7 +13583,7 @@ mips16_macro (struct mips_cl_insn *ip)
case M_SUBU_I: case M_SUBU_I:
do_subu: do_subu:
imm_expr.X_add_number = -imm_expr.X_add_number; imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]); macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
break; break;
case M_SUBU_I_2: case M_SUBU_I_2:

5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
2016-12-23 Maciej W. Rozycki <macro@imgtec.com> 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* opcode/mips.h (INSN2_SHORT_ONLY): New macro. * opcode/mips.h (INSN2_SHORT_ONLY): New macro.

10
include/opcode/mips.h
View File

@ -1803,7 +1803,7 @@ extern int bfd_mips_num_opcodes;
"Z" 3 bit register (MIPS16OP_*_MOVE32Z) "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
"v" 3 bit same register as source and destination (MIPS16OP_*_RX) "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
"w" 3 bit same register as source and destination (MIPS16OP_*_RY) "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
"0" zero register ($0) "." zero register ($0)
"S" stack pointer ($sp or $29) "S" stack pointer ($sp or $29)
"P" program counter "P" program counter
"R" return address register ($ra or $31) "R" return address register ($ra or $31)
@ -1823,8 +1823,8 @@ extern int bfd_mips_num_opcodes;
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
"F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
@ -1844,9 +1844,9 @@ extern int bfd_mips_num_opcodes;
"M" 7 bit register list for restore instruction (18 bit extended) "M" 7 bit register list for restore instruction (18 bit extended)
Characters used so far, for quick reference when adding more: Characters used so far, for quick reference when adding more:
" 456 8 0" " 56 8 "
"[]<" ".[]<"
"ABCDE HI KLM P RS UVWXYZ" "ABCDEF HI KLM P RS UVWXYZ"
"a e ijklm pq vwxyz" "a e ijklm pq vwxyz"
*/ */

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
2016-12-23 Maciej W. Rozycki <macro@imgtec.com> 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix

31
opcodes/mips16-opc.c
View File

@ -49,7 +49,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
{ {
switch (type) switch (type)
{ {
case '0': MAPPED_REG (0, 0, GP, reg_0_map); case '.': MAPPED_REG (0, 0, GP, reg_0_map);
case '6': UINT (6, 5); case '6': UINT (6, 5);
case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST); case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
@ -80,7 +81,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case '[': UINT (6, 0); case '[': UINT (6, 0);
case ']': UINT (6, 0); case ']': UINT (6, 0);
case '4': SINT (15, 0);
case '5': SINT (16, 0); case '5': SINT (16, 0);
case '8': SINT (16, 0); case '8': SINT (16, 0);
@ -89,6 +89,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case 'C': SINT (16, 0); case 'C': SINT (16, 0);
case 'D': SINT (16, 0); case 'D': SINT (16, 0);
case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE); case 'E': PCREL (16, 0, TRUE, 0, 2, FALSE, FALSE);
case 'F': SINT (15, 0);
case 'H': SINT (16, 0); case 'H': SINT (16, 0);
case 'K': SINT (16, 0); case 'K': SINT (16, 0);
case 'U': UINT (16, 0); case 'U': UINT (16, 0);
@ -107,7 +108,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case '[': INT_ADJ (3, 2, 8, 0, FALSE); case '[': INT_ADJ (3, 2, 8, 0, FALSE);
case ']': INT_ADJ (3, 8, 8, 0, FALSE); case ']': INT_ADJ (3, 8, 8, 0, FALSE);
case '4': SINT (4, 0);
case '5': UINT (5, 0); case '5': UINT (5, 0);
case '8': UINT (8, 0); case '8': UINT (8, 0);
@ -116,6 +116,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */ case 'C': INT_ADJ (8, 0, 255, 3, FALSE); /* (0 .. 255) << 3 */
case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */ case 'D': INT_ADJ (5, 0, 31, 3, FALSE); /* (0 .. 31) << 3 */
case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE); case 'E': PCREL (5, 0, FALSE, 2, 2, FALSE, FALSE);
case 'F': SINT (4, 0);
case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */ case 'H': INT_ADJ (5, 0, 31, 1, FALSE); /* (0 .. 31) << 1 */
case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */ case 'K': INT_ADJ (8, 0, 127, 3, FALSE); /* (-128 .. 127) << 3 */
case 'U': UINT (8, 0); case 'U': UINT (8, 0);
@ -184,14 +185,14 @@ const struct mips_opcode mips16_opcodes[] =
{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */ {"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */
{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, {"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 },
{"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, {"addu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
@ -228,33 +229,33 @@ const struct mips_opcode mips16_opcodes[] =
{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, {"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 },
{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, {"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
{"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, {"daddiu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, {"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, {"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, {"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 },
{"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "y,x,F", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, {"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, {"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, {"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"div", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, {"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"divu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, {"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, {"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, {"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, {"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 },
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"drem", ".,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, {"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 },
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, {"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 },
{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, {"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
@ -315,9 +316,9 @@ const struct mips_opcode mips16_opcodes[] =
{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, {"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, {"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 },
{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"rem", ".,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, {"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"remu", ".,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 },
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, {"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, {"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },