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* mips/vr4320.igen: Mark the insn in here as vr4320 only.

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Reorder the insns.
This commit is contained in:
Gavin Romig-Koch
1998-03-09 20:22:45 +00:00
parent c391655e30
commit d843d7ca34
2 changed files with 79 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
sim/.Sanitize
View File

@ -151,6 +151,34 @@ else
done done
fi fi
vr4320_files="ChangeLog"
if ( echo $* | grep keep\-vr4320 > /dev/null ) ; then
for i in $vr4320_files ; do
if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Keeping vr4320 stuff in $i
fi
fi
done
else
for i in $vr4320_files ; do
if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then
if [ -n "${verbose}" ] ; then
echo Removing traces of \"vr4320\" from $i...
fi
cp $i new
sed '/start\-sanitize\-vr4320/,/end-\sanitize\-vr4320/d' < $i > new
if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
if [ -n "${verbose}" ] ; then
echo Caching $i in .Recover...
fi
mv $i .Recover
fi
mv new $i
fi
done
fi
for i in * ; do for i in * ; do
if test ! -d $i && (grep sanitize $i > /dev/null) ; then if test ! -d $i && (grep sanitize $i > /dev/null) ; then
echo '***' Some mentions of Sanitize are still left in $i! 1>&2 echo '***' Some mentions of Sanitize are still left in $i! 1>&2

94
sim/mips/vr4320.igen
View File

@ -47,43 +47,6 @@
// Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00100,101000::::MUL
"mul r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00101,101000::::MULU
"mulu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Multiply, Accumulate // Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101000::::MAC 000000,5.RS,5.RT,00000,00000,101000::::MAC
"mac r<RS>, r<RT>" "mac r<RS>, r<RT>"
@ -95,15 +58,60 @@
// D-Multiply, Accumulate // D-Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101001::::DMAC 000000,5.RS,5.RT,00000,00000,101001::::DMAC
"dmac r<RS>, r<RT>" "dmac r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV: *vr4320:
{ {
LO = MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]); LO = 99 + SignedMultiply (SD_, GPR[RS], GPR[RT]);
} }
// Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00100,101000::::MUL
"mul r<RD>, r<RS>, r<RT>"
*vr4320:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00101,101000::::MULU
"mulu r<RD>, r<RS>, r<RT>"
*vr4320:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}
// Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
*vr4320:
{
SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Unsigned Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
*vr4320:
{
SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}
// Multiply, Accumulate and Move LO. // Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00010,101000::::MACC 000000,5.RS,5.RT,5.RD,00010,101000::::MACC
"macc r<RD>, r<RS>, r<RT>" "macc r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV: *vr4320:
{ {
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
@ -112,7 +120,7 @@
// Unsigned Multiply, Accumulate and Move LO. // Unsigned Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00011,101000::::MACCU 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
"maccu r<RD>, r<RS>, r<RT>" "maccu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV: *vr4320:
{ {
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
@ -121,7 +129,7 @@
// Multiply, Accumulate and Move HI. // Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
"macchi r<RD>, r<RS>, r<RT>" "macchi r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV: *vr4320:
{ {
SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_)); GPR[RD] = High32Bits (SD_, MulAcc (SD_));
@ -130,7 +138,7 @@
// Unsigned Multiply, Accumulate and Move HI. // Unsigned Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>" "macchiu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV: *vr4320:
{ {
SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
GPR[RD] = High32Bits (SD_, MulAcc (SD_)); GPR[RD] = High32Bits (SD_, MulAcc (SD_));