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Power10 VSX PCV generate operations

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opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
	xxgenpcvwm, xxgenpcvdm.
gas/
	* testsuite/gas/ppc/genpcv.d,
	* testsuite/gas/ppc/genpcv.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
This commit is contained in:
Alan Modra
2020-05-11 09:43:15 +09:30
parent fdefed7c26
commit d7e97a765e
6 changed files with 36 additions and 0 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/genpcv.d,
* testsuite/gas/ppc/genpcv.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 Alan Modra <amodra@gmail.com> 2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/maskmanip.d, * testsuite/gas/ppc/maskmanip.d,

14
gas/testsuite/gas/ppc/genpcv.d Normal file
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@ -0,0 +1,14 @@
#as: -mpower10
#objdump: -dr -Mpower10
#name: PCV generate operations
.*
Disassembly of section \.text:
0+0 <_start>:
.*: (f2 03 7f 29|29 7f 03 f2) xxgenpcvbm vs48,v15,3
.*: (f0 02 3f 2b|2b 3f 02 f0) xxgenpcvhm vs32,v7,2
.*: (f2 01 1f 68|68 1f 01 f2) xxgenpcvwm vs16,v3,1
.*: (f1 00 0f 6a|6a 0f 00 f1) xxgenpcvdm vs8,v1,0

6
gas/testsuite/gas/ppc/genpcv.s Normal file
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@ -0,0 +1,6 @@
.text
_start:
xxgenpcvbm 48,15,3
xxgenpcvhm 32,7,2
xxgenpcvwm 16,3,1
xxgenpcvdm 8,1,0

1
gas/testsuite/gas/ppc/ppc.exp
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@ -139,3 +139,4 @@ run_dump_test "int128"
run_dump_test "simd_perm" run_dump_test "simd_perm"
run_dump_test "outerprod" run_dump_test "outerprod"
run_dump_test "maskmanip" run_dump_test "maskmanip"
run_dump_test "genpcv"

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-05-11 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
xxgenpcvwm, xxgenpcvdm.
2020-05-11 Alan Modra <amodra@gmail.com> 2020-05-11 Alan Modra <amodra@gmail.com>
* ppc-opc.c (MP, VXVAM_MASK): Define. * ppc-opc.c (MP, VXVAM_MASK): Define.

4
opcodes/ppc-opc.c
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@ -8038,11 +8038,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
{"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
{"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},