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Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>

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* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
This commit is contained in:
Martin Hunt
1996-08-29 00:35:11 +00:00
parent e7dd77751d
commit d70b4d426b
4 changed files with 222 additions and 70 deletions
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19
sim/d10v/ChangeLog
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@ -1,3 +1,22 @@
Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
Mon Aug 26 18:30:28 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v_sim.h (SEXT32): Added.
* interp.c: Commented out printfs.
* simops.c: Fixed error in sb and st2w.
Thu Aug 15 13:30:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c, simops.c: Added remaining
DSP instructions. Added modulo addressing.
Sun Aug 11 12:57:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c, simops.c: Snapshot.
Fri Aug 2 17:44:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> Fri Aug 2 17:44:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v_sim.h, simops.c: Snapshot. * d10v_sim.h, simops.c: Snapshot.

10
sim/d10v/Makefile.in
View File

@ -56,7 +56,7 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
AR = @AR@ AR = @AR@
AR_FLAGS = rc AR_FLAGS = rc
CC = @CC@ CC = @CC@
CFLAGS = @CFLAGS@ CFLAGS = @CFLAGS@ @DEFS@
MAKEINFO = makeinfo MAKEINFO = makeinfo
RANLIB = @RANLIB@ RANLIB = @RANLIB@
CC_FOR_BUILD = @CC_FOR_BUILD@ CC_FOR_BUILD = @CC_FOR_BUILD@
@ -77,7 +77,7 @@ CSEARCH = -I. -I$(srcdir) -I../../include \
-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh -I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh
DEP = mkdep DEP = mkdep
all: run all: run libsim.a
run: interp.o $(X) run.o table.o callback.o simops.o run: interp.o $(X) run.o table.o callback.o simops.o
$(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm $(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm
@ -86,7 +86,7 @@ interp.o:interp.c table.c
run.o:run.c run.o:run.c
libsim.a:interp.o table.o simops.o libsim.a:interp.o table.o simops.o
$(AR) $(ARFLAGS) libsim.a interp.o table.o $(AR) $(ARFLAGS) libsim.a interp.o table.o simops.o
$(RANLIB) libsim.a $(RANLIB) libsim.a
simops.h: gencode simops.h: gencode
@ -95,7 +95,7 @@ simops.h: gencode
table.c: gencode simops.h table.c: gencode simops.h
./gencode >$@ ./gencode >$@
gencode: gencode.c gencode: gencode.c ../../opcodes/libopcodes.a
$(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc $(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc
.c.o: .c.o:
@ -114,7 +114,7 @@ TAGS: force
clean: clean:
rm -f *.[oa] *~ core *.E *.p *.ip aout-params.h gen-aout rm -f *.[oa] *~ core *.E *.p *.ip aout-params.h gen-aout
rm -f run libsim.a rm -f run table.c simops.h gencode libsim.a
distclean mostlyclean maintainer-clean realclean: clean distclean mostlyclean maintainer-clean realclean: clean
rm -f TAGS rm -f TAGS

35
sim/d10v/d10v_sim.h
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@ -81,6 +81,12 @@ extern struct simops Simops[];
/* sign extend a 40 bit number */ /* sign extend a 40 bit number */
#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL) #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
/* sign extend a 44 bit number */
#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
/* sign extend a 60 bit number */
#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
#define MAX32 0x7fffffffLL #define MAX32 0x7fffffffLL
#define MIN32 0xff80000000LL #define MIN32 0xff80000000LL
#define MASK32 0xffffffffLL #define MASK32 0xffffffffLL
@ -93,17 +99,28 @@ extern struct simops Simops[];
#ifdef WORDS_BIGENDIAN #ifdef WORDS_BIGENDIAN
#define RW(x) (*((uint16 *)((x)+State.imem))) #define RW(x) (*((uint16 *)((x)+State.imem)))
#define RLW(x) (*((uint32 *)((x)+State.imem))) #define RLW(x) (*((uint32 *)((x)+State.imem)))
#define SW(addr,data) RW(addr)=data #define SW(addr,data) RW(addr)=data
#define READ_16(x) (*((int16 *)(x)))
#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
#define READ_64(x) (*((int64 *)(x)))
#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
#else #else
uint32 get_longword_swap PARAMS ((uint16 x)); uint32 get_longword PARAMS ((uint8 *));
uint16 get_word_swap PARAMS ((uint16 x)); uint16 get_word PARAMS ((uint8 *));
void write_word_swap PARAMS ((uint16 addr, uint16 data)); int64 get_longlong PARAMS ((uint8 *));
#define SW(addr,data) write_word_swap(addr,data) void write_word PARAMS ((uint8 *addr, uint16 data));
#define RW(x) get_word_swap(x) void write_longlong PARAMS ((uint8 *addr, int64 data));
#define RLW(x) get_longword_swap(x)
#define SW(addr,data) write_word((long)(addr)+State.imem,data)
#define RW(x) get_word((long)(x)+State.imem)
#define RLW(x) get_longword((long)(x)+State.imem)
#define READ_16(x) get_word(x)
#define WRITE_16(addr,data) write_word(addr,data)
#define READ_64(x) get_longlong(x)
#define WRITE_64(addr,data) write_longlong(addr,data)
#endif /* not WORDS_BIGENDIAN */ #endif /* not WORDS_BIGENDIAN */

228
sim/d10v/interp.c
View File

@ -1,3 +1,4 @@
#include <signal.h>
#include "sysdep.h" #include "sysdep.h"
#include "bfd.h" #include "bfd.h"
#include "remote-sim.h" #include "remote-sim.h"
@ -59,30 +60,56 @@ lookup_hash (ins, size)
} }
uint32 uint32
get_longword_swap (x) get_longword (x)
uint16 x; uint8 *x;
{ {
uint8 *a = (uint8 *)(x + State.imem); uint8 *a = x;
return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]); return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]);
} }
uint16 int64
get_word_swap (x) get_longlong (x)
uint16 x; uint8 *x;
{ {
uint8 *a = (uint8 *)(x + State.imem); uint8 *a = x;
return (a[0]<<8) + a[1]; return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) +
((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7];
}
uint16
get_word (x)
uint8 *x;
{
uint8 *a = x;
return ((uint16)a[0]<<8) + a[1];
} }
void void
write_word_swap (addr, data) write_word (addr, data)
uint16 addr, data; uint8 *addr;
uint16 data;
{ {
uint8 *a = (uint8 *)(addr + State.imem); uint8 *a = addr;
a[0] = data >> 8; a[0] = data >> 8;
a[1] = data & 0xff; a[1] = data & 0xff;
} }
void
write_longlong (addr, data)
uint8 *addr;
int64 data;
{
uint8 *a = addr;
a[0] = data >> 56;
a[1] = (data >> 48) & 0xff;
a[2] = (data >> 40) & 0xff;
a[3] = (data >> 32) & 0xff;
a[4] = (data >> 24) & 0xff;
a[5] = (data >> 16) & 0xff;
a[6] = (data >> 8) & 0xff;
a[7] = data & 0xff;
}
static void static void
get_operands (struct simops *s, uint32 ins) get_operands (struct simops *s, uint32 ins)
@ -127,26 +154,35 @@ do_parallel (ins1, ins2)
uint16 ins1, ins2; uint16 ins1, ins2;
{ {
struct hash_entry *h1, *h2; struct hash_entry *h1, *h2;
/* printf ("do_parallel %x || %x\n",ins1,ins2); */ /* printf ("do_parallel %x || %x\n",ins1,ins2); */
h1 = lookup_hash (ins1, 0); h1 = lookup_hash (ins1, 0);
get_operands (h1->ops, ins1);
h2 = lookup_hash (ins2, 0); h2 = lookup_hash (ins2, 0);
get_operands (h2->ops, ins2);
if (h1->ops->exec_type == PARONLY) if (h1->ops->exec_type == PARONLY)
{ {
get_operands (h1->ops, ins1);
(h1->ops->func)(); (h1->ops->func)();
if (State.exe) if (State.exe)
(h2->ops->func)(); {
get_operands (h2->ops, ins2);
(h2->ops->func)();
}
} }
else if (h2->ops->exec_type == PARONLY) else if (h2->ops->exec_type == PARONLY)
{ {
get_operands (h2->ops, ins2);
(h2->ops->func)(); (h2->ops->func)();
if (State.exe) if (State.exe)
(h1->ops->func)(); {
get_operands (h1->ops, ins1);
(h1->ops->func)();
}
} }
else else
{ {
get_operands (h1->ops, ins1);
(h1->ops->func)(); (h1->ops->func)();
get_operands (h2->ops, ins2);
(h2->ops->func)(); (h2->ops->func)();
} }
} }
@ -190,7 +226,7 @@ sim_write (addr, buffer, size)
int i; int i;
init_system (); init_system ();
printf ("sim_write %d bytes to 0x%x\n",size,addr); /* printf ("sim_write %d bytes to 0x%x\n",size,addr); */
for (i = 0; i < size; i++) for (i = 0; i < size; i++)
{ {
State.imem[i+addr] = buffer[i]; State.imem[i+addr] = buffer[i];
@ -257,44 +293,50 @@ sim_resume (step, siggnal)
int i; int i;
reg_t oldpc; reg_t oldpc;
printf ("sim_resume %d %d\n",step,siggnal); /* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
while (1) if (step)
{ State.exception = SIGTRAP;
inst = RLW (PC << 2); else
oldpc = PC; State.exception = 0;
switch (inst & 0xC0000000)
{ do
case 0xC0000000: {
/* long instruction */ inst = RLW (PC << 2);
do_long (inst & 0x3FFFFFFF); oldpc = PC;
break; switch (inst & 0xC0000000)
case 0x80000000: {
/* R -> L */ case 0xC0000000:
do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15); /* long instruction */
break; do_long (inst & 0x3FFFFFFF);
case 0x40000000: break;
/* L -> R */ case 0x80000000:
do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); /* R -> L */
break; do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
case 0: break;
do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); case 0x40000000:
break; /* L -> R */
} do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
break;
if (State.RP && PC == RPT_E) case 0:
{ do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
RPT_C -= 1; break;
if (RPT_C == 0) }
State.RP = 0;
else if (State.RP && PC == RPT_E)
PC = RPT_S; {
} RPT_C -= 1;
if (RPT_C == 0)
/* FIXME */ State.RP = 0;
if (PC == oldpc) else
PC++; PC = RPT_S;
} }
/* FIXME */
if (PC == oldpc)
PC++;
}
while (!State.exception);
} }
int int
@ -308,7 +350,7 @@ void
sim_info (verbose) sim_info (verbose)
int verbose; int verbose;
{ {
printf ("sim_verbose\n"); printf ("sim_info\n");
} }
void void
@ -341,5 +383,79 @@ sim_stop_reason (reason, sigrc)
enum sim_stop *reason; enum sim_stop *reason;
int *sigrc; int *sigrc;
{ {
printf ("sim_stop_reason\n"); /* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */
if (State.exception == SIGQUIT)
{
*reason = sim_exited;
*sigrc = State.exception;
}
else
{
*reason = sim_stopped;
*sigrc = State.exception;
}
} }
void
sim_fetch_register (rn, memory)
int rn;
unsigned char *memory;
{
if (rn > 31)
{
WRITE_64 (memory, State.a[rn-32]);
/* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
}
else
{
WRITE_16 (memory, State.regs[rn]);
/* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
}
}
void
sim_store_register (rn, memory)
int rn;
unsigned char *memory;
{
if (rn > 31)
{
State.a[rn-32] = READ_64 (memory) & MASK40;
/* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
}
else
{
State.regs[rn]= READ_16 (memory);
/* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */
}
}
sim_read (addr, buffer, size)
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
int i;
for (i = 0; i < size; i++)
{
buffer[i] = State.imem[addr + i];
}
return size;
}
void
sim_do_command (cmd)
char *cmd;
{
printf("sim_do_command: %s\n",cmd);
}
int
sim_load (prog, from_tty)
char *prog;
int from_tty;
{
/* Return nonzero so GDB will handle it. */
return 1;
}