espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-19 09:14:14 +08:00
Code Issues Packages Projects Releases Wiki Activity

gas/

Browse Source 
* config/tc-sparc.c (sparc_arch_types): Add leon.
	(sparc_arch): Move sparc4 around and add leon.
	(sparc_target_format): Document -Aleon.
	* doc/c-sparc.texi: Likewise.
include/
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON.
opcodes/
	* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
	bfd_mach_sparc.
	* sparc-opc.c (MASK_LEON): Define.
	(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
	(letandleon): New macro.
	(v9andleon): Likewise.
	(sparc_opc): Add leon.
	(umac): Enable for letandleon.
	(smac): Likewise.
	(casa): Enable for v9andleon.
	(cas): Likewise.
	(casl): Likewise.
This commit is contained in:
Eric Botcazou
2013-08-05 16:11:07 +00:00
parent 303a26609a
commit d6787ef95c
8 changed files with 58 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
Konrad Eisele <konrad@gaisler.com>
* config/tc-sparc.c (sparc_arch_types): Add leon.
(sparc_arch): Move sparc4 around and add leon.
(sparc_target_format): Document -Aleon.
* doc/c-sparc.texi: Likewise.
2013-08-05 Richard Sandiford <rdsandiford@googlemail.com> 2013-08-05 Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (mips_lookup_insn): Make length and opend signed. * config/tc-mips.c (mips_lookup_insn): Make length and opend signed.

7
gas/config/tc-sparc.c
View File

@ -221,7 +221,7 @@ static void output_insn (const struct sparc_opcode *, struct sparc_it *);
for this use. That table is for opcodes only. This table is for opcodes for this use. That table is for opcodes only. This table is for opcodes
and file formats. */ and file formats. */
enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
v8plusa, v9, v9a, v9b, v9_64}; v8plusa, v9, v9a, v9b, v9_64};
static struct sparc_arch { static struct sparc_arch {
@ -245,8 +245,9 @@ static struct sparc_arch {
{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF }, { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA }, { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
{ "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
{ "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU }, { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
{ "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
{ "leon", "leon", leon, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
@ -363,7 +364,7 @@ sparc_target_format (void)
* -bump * -bump
* Warn on architecture bumps. See also -A. * Warn on architecture bumps. See also -A.
* *
* -Av6, -Av7, -Av8, -Asparclite, -Asparclet * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
* Standard 32 bit architectures. * Standard 32 bit architectures.
* -Av9, -Av9a, -Av9b * -Av9, -Av9a, -Av9b
* Sparc64 in either a 32 or 64 bit world (-32/-64 says which). * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).

3
gas/doc/c-sparc.texi
View File

@ -54,6 +54,7 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
@kindex -Av6 @kindex -Av6
@kindex -Av7 @kindex -Av7
@kindex -Av8 @kindex -Av8
@kindex -Aleon
@kindex -Asparclet @kindex -Asparclet
@kindex -Asparclite @kindex -Asparclite
@kindex -Av9 @kindex -Av9
@ -69,7 +70,7 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
@kindex -Asparcima @kindex -Asparcima
@kindex -Asparcvis3 @kindex -Asparcvis3
@kindex -Asparcvis3r @kindex -Asparcvis3r
@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima

5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
Konrad Eisele <konrad@gaisler.com>
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON.
2013-06-08 Catherine Moore <clm@codesourcery.com> 2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field. * opcode/mips.h (mips_opcode): Add ase field.

1
include/opcode/sparc.h
View File

@ -42,6 +42,7 @@ enum sparc_opcode_arch_val
SPARC_OPCODE_ARCH_V6 = 0, SPARC_OPCODE_ARCH_V6 = 0,
SPARC_OPCODE_ARCH_V7, SPARC_OPCODE_ARCH_V7,
SPARC_OPCODE_ARCH_V8, SPARC_OPCODE_ARCH_V8,
SPARC_OPCODE_ARCH_LEON,
SPARC_OPCODE_ARCH_SPARCLET, SPARC_OPCODE_ARCH_SPARCLET,
SPARC_OPCODE_ARCH_SPARCLITE, SPARC_OPCODE_ARCH_SPARCLITE,
/* V9 variants must appear last. */ /* V9 variants must appear last. */

16
opcodes/ChangeLog
View File

@ -1,3 +1,19 @@
2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
Konrad Eisele <konrad@gaisler.com>
* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
bfd_mach_sparc.
* sparc-opc.c (MASK_LEON): Define.
(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
(letandleon): New macro.
(v9andleon): Likewise.
(sparc_opc): Add leon.
(umac): Enable for letandleon.
(smac): Likewise.
(casa): Enable for v9andleon.
(cas): Likewise.
(casl): Likewise.
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com> Richard Sandiford <rdsandiford@googlemail.com>

3
opcodes/sparc-dis.c
View File

@ -223,7 +223,8 @@ compute_arch_mask (unsigned long mach)
{ {
case 0 : case 0 :
case bfd_mach_sparc : case bfd_mach_sparc :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
| SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
case bfd_mach_sparc_sparclet : case bfd_mach_sparc_sparclet :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
case bfd_mach_sparc_sparclite : case bfd_mach_sparc_sparclite :

32
opcodes/sparc-opc.c
View File

@ -33,6 +33,7 @@
#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
@ -41,12 +42,13 @@
/* Bit masks of architectures supporting the insn. */ /* Bit masks of architectures supporting the insn. */
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B)
/* v6 insns not supported on the sparclet. */ /* v6 insns not supported on the sparclet. */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ #define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* Although not all insns are implemented in hardware, sparclite is defined /* Although not all insns are implemented in hardware, sparclite is defined
to be a superset of v8. Unimplemented insns trap and are then theoretically to be a superset of v8. Unimplemented insns trap and are then theoretically
@ -54,15 +56,19 @@
It's not clear that the same is true for sparclet, although the docs It's not clear that the same is true for sparclet, although the docs
suggest it is. Rather than complicating things, the sparclet assembler suggest it is. Rather than complicating things, the sparclet assembler
recognizes all v8 insns. */ recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B) | MASK_V9 | MASK_V9A | MASK_V9B)
#define sparclet (MASK_SPARCLET) #define sparclet (MASK_SPARCLET)
/* sparclet insns supported by leon. */
#define letandleon (MASK_SPARCLET | MASK_LEON)
#define sparclite (MASK_SPARCLITE) #define sparclite (MASK_SPARCLITE)
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
#define v9a (MASK_V9A | MASK_V9B) #define v9a (MASK_V9A | MASK_V9B)
#define v9b (MASK_V9B) #define v9b (MASK_V9B)
/* v9 insns supported by leon. */
#define v9andleon (MASK_V9 | MASK_LEON)
/* v6 insns not supported by v9. */ /* v6 insns not supported by v9. */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLET | MASK_SPARCLITE) | MASK_SPARCLET | MASK_SPARCLITE)
/* v9a instructions which would appear to be aliases to v9's impdep's /* v9a instructions which would appear to be aliases to v9's impdep's
otherwise. */ otherwise. */
@ -76,6 +82,7 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
{ "v6", MASK_V6 }, { "v6", MASK_V6 },
{ "v7", MASK_V6 | MASK_V7 }, { "v7", MASK_V6 | MASK_V7 },
{ "v8", MASK_V6 | MASK_V7 | MASK_V8 }, { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
{ "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON },
{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
/* ??? Don't some v8 priviledged insns conflict with v9? */ /* ??? Don't some v8 priviledged insns conflict with v9? */
@ -1728,8 +1735,9 @@ EFPOP2_2 ("efcmpes", 0x055, "e,f"),
/* sparclet specific insns */ /* sparclet specific insns */
COMMUTEOP ("umac", 0x3e, sparclet), COMMUTEOP ("umac", 0x3e, letandleon),
COMMUTEOP ("smac", 0x3f, sparclet), COMMUTEOP ("smac", 0x3f, letandleon),
COMMUTEOP ("umacd", 0x2e, sparclet), COMMUTEOP ("umacd", 0x2e, sparclet),
COMMUTEOP ("smacd", 0x2f, sparclet), COMMUTEOP ("smacd", 0x2f, sparclet),
COMMUTEOP ("umuld", 0x09, sparclet), COMMUTEOP ("umuld", 0x09, sparclet),
@ -1780,8 +1788,8 @@ SLCBCC("cbnefr", 15),
#undef SLCBCC2 #undef SLCBCC2
#undef SLCBCC #undef SLCBCC
{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9 }, { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9andleon },
{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9 }, { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9andleon },
{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 }, { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 },
{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 }, { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 },
@ -1791,8 +1799,8 @@ SLCBCC("cbnefr", 15),
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */ { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */ { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */ { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */
{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */ { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P,rs2,rd */
{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P_L,rs2,rd */
{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */