mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-08-06 14:49:38 +08:00
Numerous fixes.
This commit is contained in:
Andrew Cagney
121
sim/tic80/insns
121
sim/tic80/insns
@ -235,32 +235,33 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// dld[{.b|.h|.d}]
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#void::function::do_dld:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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# sim_io_error ("dld");
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void::function::do_dld:instruction_address cia, int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld (_SD, cia, Dest, Base, rBase, m, sz, S, Offset);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
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# do_dld (_SD, rDest, rSource1, rSource2);
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do_dld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
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# long_immediate (LongSignedImmediateOffset);
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# do_dld (_SD, rDest, LongSignedImmediate, rSource2);
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long_immediate (LongSignedImmediateOffset);
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do_dld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// dld.u[{.b|.h|.d}]
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#void::function::do_dld_u:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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# sim_io_error ("dld.u");
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void::function::do_dld_u:instruction_address cia, unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld_u (_SD, cia, rDest, Base, rBase, m, sz, S, Offset);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
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# do_dld_u (_SD, rDest, rSource1, rSource2);
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do_dld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
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# long_immediate (LongSignedImmediateOffset);
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# do_dld_u (_SD, rDest, LongSignedImmediate, rSource2);
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long_immediate (LongSignedImmediateOffset);
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do_dld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// dst[{.b|.h|.d}]
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#void::function::do_dst:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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# sim_io_error ("dst");
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31.Dest,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
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# do_dst (_SD, rDest, rSource1, rSource2);
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31.Dest,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
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# do_dst (_SD, rDest, LongSignedImmediate, rSource2);
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void::function::do_dst:instruction_address cia, int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_st (_SD, cia, Source, Base, rBase, m, sz, S, Offset);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
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do_dst (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
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long_immediate (LongSignedImmediateOffset);
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do_dst (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// estop
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@ -386,7 +387,10 @@ instruction_address::function::do_jsr:instruction_address cia, instruction_addre
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}
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else
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*rLink = cia.dp + sizeof (instruction_word);
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nia.dp = cia.ip + 4 * offset;
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nia.dp = offset + base;
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if (nia.dp & 0x3)
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engine_error (SD, CPU, cia, "destination address 0x%lx misaligned",
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(unsigned long) nia.dp);
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return nia;
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31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
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nia = do_jsr (_SD, cia, nia, rLink, A, vSignedOffset, rBase);
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@ -398,40 +402,48 @@ instruction_address::function::do_jsr:instruction_address cia, instruction_addre
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// ld[{.b.h.d}]
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void::function::do_ld:instruction_address cia, unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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void::function::do_ld:instruction_address cia, int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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switch (sz)
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{
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case 0:
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addr = Base + (S ? (Offset << 0) : Offset);
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*rDest = MEM (signed, addr, 1);
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if (m)
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*rBase = addr;
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GPR(Dest) = MEM (signed, addr, 1);
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break;
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case 1:
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addr = Base + (S ? (Offset << 1) : Offset);
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*rDest = MEM (signed, addr, 2);
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if (m)
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*rBase = addr;
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GPR(Dest) = MEM (signed, addr, 2);
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break;
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case 2:
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addr = Base + (S ? (Offset << 2) : Offset);
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*rDest = MEM (signed, addr, 4);
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if (m)
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*rBase = addr;
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GPR(Dest) = MEM (signed, addr, 4);
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break;
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case 3:
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engine_error (SD, CPU, cia, "ld.d broken");
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if (Dest & 0x1)
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engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
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cia.ip, Dest);
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addr = Base + (S ? (Offset << 3) : Offset);
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*rDest = MEM (signed, addr, 8);
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if (m)
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*rBase = addr;
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*(unsigned64*)(&GPR(Dest)) = MEM (signed, addr, 8);
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break;
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default:
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addr = -1;
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engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
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}
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if (m)
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*rBase = addr;
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31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
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do_ld (_SD, cia, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
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do_ld (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
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long_immediate (LongSignedImmediateOffset);
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do_ld (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// ld.u[{.b.h.d}]
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@ -514,9 +526,16 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// rdcr
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void::function::do_rdcr:instruction_address cia, unsigned32 Dest, int cr
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if (Dest != 0)
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engine_error (SD, CPU, cia, "rdcr unimplement");
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31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
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do_rdcr (_SD, cia, Dest, UCRN);
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31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
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do_rdcr (_SD, cia, Dest, UCRN);
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31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
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long_immediate (UnsignedControlRegisterNumber);
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do_rdcr (_SD, cia, Dest, UnsignedControlRegisterNumber);
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// rmo
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@ -559,40 +578,42 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// st[{.b|.h|.d}]
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void::function::do_st:instruction_address cia, unsigned32 rSource, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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void::function::do_st:instruction_address cia, int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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switch (sz)
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{
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case 0:
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addr = Base + (S ? (Offset << 0) : Offset);
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STORE (addr, 1, rSource);
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STORE (addr, 1, GPR(Source));
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break;
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case 1:
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addr = Base + (S ? (Offset << 1) : Offset);
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STORE (addr, 2, rSource);
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STORE (addr, 2, GPR(Source));
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break;
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case 2:
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addr = Base + (S ? (Offset << 2) : Offset);
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STORE (addr, 4, rSource);
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STORE (addr, 4, GPR(Source));
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break;
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case 3:
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engine_error (SD, CPU, cia, "st.d broken");
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if (Source & 0x1)
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engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
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cia.ip, Source);
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addr = Base + (S ? (Offset << 3) : Offset);
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STORE (addr, 8, rSource);
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STORE (addr, 8, *(unsigned64*)&GPR(Source));
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break;
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default:
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addr = -1;
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engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
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engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
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}
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if (m)
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*rBase = addr;
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31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
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do_st (_SD, cia, rSource, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
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do_st (_SD, cia, rSource, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
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long_immediate (LongSignedImmediateOffset);
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do_st (_SD, cia, rSource, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// sub
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@ -600,7 +621,6 @@ void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
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ALU_BEGIN (Source1);
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ALU_SUB (Source2);
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ALU_END (*rDest);
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// FIXME - the book has 15.1 which conflicts with subu.
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31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
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do_sub (_SD, rDest, vSource1, rSource2);
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31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
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@ -613,6 +633,7 @@ void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
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// subu
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void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2
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*rDest = Source1 - Source2;
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// NOTE - the book has 15.1 which conflicts with subu.
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31.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i
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do_subu (_SD, rDest, vSource1, rSource2);
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31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
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@ -634,32 +655,36 @@ void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2
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// trap
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void::function::do_trap:instruction_address cia, unsigned32 trap_number
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if (trap_number == 72)
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switch (trap_number)
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{
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switch (GPR(2))
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case 72:
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switch (GPR(15))
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{
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case 1: /* EXIT */
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{
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engine_halt (SD, CPU, cia, sim_exited, GPR(3));
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engine_halt (SD, CPU, cia, sim_exited, GPR(2));
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break;
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}
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case 4: /* WRITE */
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{
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int i;
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if (GPR(3) != 1)
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engine_error (SD, CPU, cia, "write to invalid fid %d", GPR(3));
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for (i = 0; i < GPR(5); i++)
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if (GPR(2) != 1)
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engine_error (SD, CPU, cia, "write to invalid fid %d", GPR(2));
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for (i = 0; i < GPR(6); i++)
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{
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char c;
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c = MEM (unsigned, GPR(4) + i, 1);
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sim_io_write_stdout (SD, &c, 1);
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}
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GPR(2) = GPR(5);
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GPR(2) = GPR(6);
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break;
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}
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default:
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engine_error (SD, CPU, cia, "unknown trap %d", GPR(2));
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engine_error (SD, CPU, cia, "unknown syscall trap %d", GPR(2));
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}
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break;
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default:
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engine_error (SD, CPU, cia, "unsupported trap %d", trap_number);
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}
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31./,27.0,26./,21.0b0000001,14.UTN::::trap i
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do_trap (_SD, cia, UTN);
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@ -676,7 +701,7 @@ void::function::do_trap:instruction_address cia, unsigned32 trap_number
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// vld{0|1}.{s|d} - see above - same instruction
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#31.Dest,26.*,21.0b11110,18.*,10.1,9.S,8.*,6.p,7.******::::vld
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#31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::::vld
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// vmac.ss{s|d}
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