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* h8300.h (UNOP3): Mark the register operand in this insn

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as a source operand, not a destination operand.
So the simulator can handle shal #2,er0 correctly.
This commit is contained in:
Jeff Law
1996-07-02 19:20:37 +00:00
parent eafdda3d8d
commit d3329f0d0c
2 changed files with 14 additions and 3 deletions
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6
include/opcode/h8300.h
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@ -208,9 +208,9 @@ struct h8_opcode
{ O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
{ O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
/* start-sanitize-h8s */\
,{ O(code,SB), 1, 2, name, {SHIFT_IMM, RD8, E}, {op1, op2, op3+4, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
{ O(code,SW), 0, 2, name, {SHIFT_IMM, RD16, E}, {op1, op2, op3+5, RD16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
{ O(code,SL), 0, 2, name, {SHIFT_IMM, RD32, E}, {op1, op2, op3+7, RD32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
,{ O(code,SB), 1, 2, name, {SHIFT_IMM, RS8, E}, {op1, op2, op3+4, RS8, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
{ O(code,SW), 0, 2, name, {SHIFT_IMM, RS16, E}, {op1, op2, op3+5, RS16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
{ O(code,SL), 0, 2, name, {SHIFT_IMM, RS32, E}, {op1, op2, op3+7, RS32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
/* end-sanitize-h8s */ \