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gas/

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2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* config/tc-mips.c (is_opcode_valid):  Build ASE mask.
	(is_opcode_valid_16): Pass ase value to opcode_is_member.
	(append_insn): Change INSN_xxxx to ASE_xxxx.

include/
2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* opcode/mips.h (mips_opcode): Add ase field.
	(INSN_ASE_MASK): Delete.
	(INSN_DSP): Rename to ASE_DSP.  Provide new value.
	(INSN_DSPR2): Rename to ASE_DSPR2.  Provide new value.
	(INSN_MCU): Rename to ASE_MCU.  Provide new value.
	(INSN_MDMX): Rename to ASE_MDMX.  Provide new value.
	(INSN_MIPS3d): Rename to ASE_MIPS3D.  Provide new value.
	(INSN_MT): Rename to ASE_MT.  Provide new value.
	(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS.  Provide new value.
	(INSN_VIRT): Rename to ASE_VIRT.  Provide new value.
	(INSN_VIRT64): Rename to ASE_VIRT64.  Provide new value.
	(opcode_is_member): Add ase argument.  Check ase.

opcodes/
2013-06-08  Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* micromips-opc.c (D32, D33, MC): Update definitions.
 	(micromips_opcodes):  Initialize ase field.
	* mips-dis.c (mips_arch_choice): Add ase field.
	(mips_arch_choices): Initialize ase field.
	(set_default_mips_dis_options): Declare and setup mips_ase.
	* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
	MT32, MC): Update definitions.
	(mips_builtin_opcodes): Initialize ase field.
This commit is contained in:
Richard Sandiford
2013-06-08 10:22:55 +00:00
parent 1edebdbff5
commit d301a56b40
8 changed files with 1017 additions and 976 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
2013-06-01 George Thomas <george.thomas@atmel.com>
* gas/config/tc-avr.c: Change ISA for devices with USB support to

31
gas/config/tc-mips.c
View File

@ -2247,37 +2247,38 @@ reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
return ok && reglist != 0;
}
/* Return TRUE if opcode MO is valid on the currently selected ISA and
architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
static bfd_boolean
is_opcode_valid (const struct mips_opcode *mo)
{
int isa = mips_opts.isa;
int ase = 0;
int fp_s, fp_d;
if (mips_opts.ase_mdmx)
isa |= INSN_MDMX;
ase |= ASE_MDMX;
if (mips_opts.ase_dsp)
isa |= INSN_DSP;
ase |= ASE_DSP;
if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
isa |= INSN_DSP64;
ase |= ASE_DSP64;
if (mips_opts.ase_dspr2)
isa |= INSN_DSPR2;
ase |= ASE_DSPR2;
if (mips_opts.ase_mt)
isa |= INSN_MT;
ase |= ASE_MT;
if (mips_opts.ase_mips3d)
isa |= INSN_MIPS3D;
ase |= ASE_MIPS3D;
if (mips_opts.ase_smartmips)
isa |= INSN_SMARTMIPS;
ase |= ASE_SMARTMIPS;
if (mips_opts.ase_mcu)
isa |= INSN_MCU;
ase |= ASE_MCU;
if (mips_opts.ase_virt)
isa |= INSN_VIRT;
ase |= ASE_VIRT;
if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
isa |= INSN_VIRT64;
ase |= ASE_VIRT64;
if (!opcode_is_member (mo, isa, mips_opts.arch))
if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
return FALSE;
/* Check whether the instruction or macro requires single-precision or
@ -2309,7 +2310,7 @@ is_opcode_valid (const struct mips_opcode *mo)
static bfd_boolean
is_opcode_valid_16 (const struct mips_opcode *mo)
{
return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
}
/* Return TRUE if the size of the microMIPS opcode MO matches one
@ -4395,7 +4396,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
&& (mips_opts.at || mips_pic == NO_PIC)
/* Don't relax BPOSGE32/64 as they have no complementing
branches. */
&& !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
&& !(ip->insn_mo->ase & (ASE_DSP64 | ASE_DSP)));
if (!HAVE_CODE_COMPRESSION
&& address_expr

15
include/ChangeLog
View File

@ -1,3 +1,18 @@
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
2013-05-06 Paul Brook <paul@codesourcery.com>
include/elf/

44
include/opcode/mips.h
View File

@ -357,6 +357,9 @@ struct mips_opcode
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
/* A collection of bits describing the ASE of which this instruction
or macro is a member. */
unsigned long ase;
/* A collection of bits describing the instruction sets of which this
instruction or macro is not a member. */
unsigned long exclusions;
@ -733,20 +736,9 @@ static const unsigned int mips_isa_table[] =
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f0d0
/* DSP ASE */
#define INSN_DSP 0x00001000
#define INSN_DSP64 0x00002000
/* MIPS R5900 instruction */
#define INSN_5900 0x00004000
/* Virtualization ASE */
#define INSN_VIRT 0x00000080
#define INSN_VIRT64 0x00000040
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00008000
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
/* LSI R4010 instruction. */
@ -768,14 +760,6 @@ static const unsigned int mips_isa_table[] =
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
/* MDMX ASE */
#define INSN_MDMX 0x04000000
/* MT ASE */
#define INSN_MT 0x08000000
/* SmartMIPS ASE */
#define INSN_SMARTMIPS 0x10000000
/* DSP R2 ASE */
#define INSN_DSPR2 0x20000000
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
@ -785,8 +769,24 @@ static const unsigned int mips_isa_table[] =
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
/* DSP ASE */
#define ASE_DSP 0x00000001
#define ASE_DSP64 0x00000002
/* DSP R2 ASE */
#define ASE_DSPR2 0x00000004
/* MCU (MicroController) ASE */
#define INSN_MCU 0x00000010
#define ASE_MCU 0x00000010
/* MDMX ASE */
#define ASE_MDMX 0x00000020
/* MIPS-3D ASE */
#define ASE_MIPS3D 0x00000040
/* MT ASE */
#define ASE_MT 0x00000080
/* SmartMIPS ASE */
#define ASE_SMARTMIPS 0x00000100
/* Virtualization ASE */
#define ASE_VIRT 0x00000200
#define ASE_VIRT64 0x00000400
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@ -923,7 +923,7 @@ cpu_is_member (int cpu, unsigned int mask)
if instruction INSN is available to the given ISA and CPU. */
static inline bfd_boolean
opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
{
if (!cpu_is_member (cpu, insn->exclusions))
{
@ -935,7 +935,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
return TRUE;
/* Test for ASE compatibility. */
if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
if ((ase & insn->ase) != 0)
return TRUE;
/* Test for processor-specific extensions. */

12
opcodes/ChangeLog
View File

@ -1,3 +1,15 @@
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
* s390-opc.txt (flogr): Require a register pair destination.

346
opcodes/micromips-opc.c
View File

@ -104,18 +104,18 @@
#define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */
#define MOD_a WR_a|RD_a
#define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 INSN_DSP
#define D33 INSN_DSPR2
#define D32 ASE_DSP
#define D33 ASE_DSPR2
/* MIPS MCU (MicroController) ASE support. */
#define MC INSN_MCU
#define MC ASE_MCU
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
/* name, args, match, mask, pinfo, pinfo2, membership, [ase], [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
@ -149,9 +149,9 @@ const struct mips_opcode micromips_opcodes[] =
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, MC },
{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
@ -184,9 +184,9 @@ const struct mips_opcode micromips_opcodes[] =
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, MC },
{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC },
{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
/* b is at the top of the table. */
/* bal is at the top of the table. */
{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
@ -525,7 +525,7 @@ const struct mips_opcode micromips_opcodes[] =
{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s, 0, I1 },
{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, MC },
{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC },
{"jr", "mj", 0x4580, 0xffe0, UBD, RD_mj, I1 },
{"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */
{"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */
@ -658,12 +658,12 @@ const struct mips_opcode micromips_opcodes[] =
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
{"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 },
{"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
@ -675,10 +675,10 @@ const struct mips_opcode micromips_opcodes[] =
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
{"mfhi", "mj", 0x4600, 0xffe0, RD_HI, WR_mj, I1 },
{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_s|RD_HI, 0, I1 },
{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s|RD_HI, 0, D32 },
{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s|RD_HI, 0, 0, D32 },
{"mflo", "mj", 0x4640, 0xffe0, RD_LO, WR_mj, I1 },
{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_s|RD_LO, 0, I1 },
{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s|RD_LO, 0, D32 },
{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s|RD_LO, 0, 0, D32 },
{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
@ -700,12 +700,12 @@ const struct mips_opcode micromips_opcodes[] =
{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
{"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 },
{"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
@ -716,9 +716,9 @@ const struct mips_opcode micromips_opcodes[] =
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 },
{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s|WR_HI, 0, D32 },
{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s|WR_HI, 0, 0, D32 },
{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 },
{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s|WR_LO, 0, D32 },
{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s|WR_LO, 0, 0, D32 },
{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
@ -729,9 +729,9 @@ const struct mips_opcode micromips_opcodes[] =
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 },
{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, 0, D32 },
{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 },
{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, 0, D32 },
{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
@ -984,159 +984,159 @@ const struct mips_opcode micromips_opcodes[] =
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* MIPS DSP ASE. */
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, D32 },
{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s|RD_t, 0, D32 },
{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA, 0, D32 },
{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t|RD_a, 0, D32 },
{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, D32 },
{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, D32 },
{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d, 0, D32 },
{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t, 0, D32 },
{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, D32 },
{"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a|RD_s, 0, D32 },
{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t|RD_s, 0, D32 },
{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t|RD_s, 0, D32 },
{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s, 0, D32 },
{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t|RD_s, 0, D32 },
{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t|RD_s, 0, D32 },
{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s, 0, D32 },
{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t|RD_s, 0, D32 },
{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t|RD_s, 0, D32 },
{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA, 0, D32 },
{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t|DSP_VOLA, 0, D32 },
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32 },
{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s|RD_t, 0, 0, D32 },
{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA, 0, 0, D32 },
{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0, 0, D32 },
{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, 0, D32 },
{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t|RD_a, 0, 0, D32 },
{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t, 0, 0, D32 },
{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA, 0, 0, D32 },
{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D32 },
{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 },
{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, 0, D32 },
{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, 0, D32 },
{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d, 0, 0, D32 },
{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t, 0, 0, D32 },
{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, 0, D32 },
{"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a|RD_s, 0, 0, D32 },
{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t|RD_s, 0, 0, D32 },
{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t|RD_s, 0, 0, D32 },
{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s, 0, 0, D32 },
{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t|RD_s, 0, 0, D32 },
{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t|RD_s, 0, 0, D32 },
{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D32 },
{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA, 0, 0, D32 },
{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t|DSP_VOLA, 0, 0, D32 },
/* MIPS DSP ASE Rev2. */
{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t|RD_s, 0, D33 },
{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
{"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s, 0, D33 },
{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t|RD_s, 0, D33 },
{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s, 0, D33 },
{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t|RD_s, 0, D33 },
{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t|RD_s, 0, 0, D33 },
{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, 0, D33 },
{"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s, 0, 0, D33 },
{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, 0, D33 },
{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D33 },
{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s, 0, 0, D33 },
{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t|RD_s, 0, 0, D33 },
{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s, 0, 0, D33 },
{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t|RD_s, 0, 0, D33 },
{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, 0, D33 },
};
const int bfd_micromips_num_opcodes =

95
opcodes/mips-dis.c
View File

@ -517,6 +517,7 @@ struct mips_arch_choice
unsigned long bfd_mach;
int processor;
int isa;
int ase;
const char * const *cp0_names;
const struct mips_cp0sel_name *cp0sel_names;
unsigned int cp0sel_names_len;
@ -525,56 +526,56 @@ struct mips_arch_choice
const struct mips_arch_choice mips_arch_choices[] =
{
{ "numeric", 0, 0, 0, 0,
{ "numeric", 0, 0, 0, 0, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
{ "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@ -583,64 +584,66 @@ const struct mips_arch_choice mips_arch_choices[] =
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
ISA_MIPS32 | INSN_SMARTMIPS,
ISA_MIPS32, ASE_SMARTMIPS,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
(ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
| INSN_MIPS3D | INSN_MT | INSN_MCU | INSN_VIRT),
ISA_MIPS32R2,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT
| ASE_MCU | ASE_VIRT),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
(ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
| INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU | INSN_VIRT | INSN_VIRT64),
ISA_MIPS64R2,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX
| ASE_MCU | ASE_VIRT | ASE_VIRT64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
mips_cp0_names_sb1,
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
mips_hwr_names_numeric },
{ "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
{ "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric,
ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric,
ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR,
ISA_MIPS64 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
mips_hwr_names_numeric },
@ -648,14 +651,14 @@ const struct mips_arch_choice mips_arch_choices[] =
/* XLP is mostly like XLR, with the prominent exception it is being
MIPS64R2. */
{ "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64R2 | INSN_XLR,
ISA_MIPS64R2 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
mips_hwr_names_numeric },
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
};
@ -664,6 +667,7 @@ const struct mips_arch_choice mips_arch_choices[] =
values. */
static int mips_processor;
static int mips_isa;
static int mips_ase;
static int micromips_ase;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
@ -769,6 +773,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
mips_isa = ISA_MIPS3;
mips_processor = CPU_R3000;
micromips_ase = 0;
mips_ase = 0;
mips_gpr_names = mips_gpr_names_oldabi;
mips_fpr_names = mips_fpr_names_numeric;
mips_cp0_names = mips_cp0_names_numeric;
@ -796,12 +801,14 @@ set_default_mips_dis_options (struct disassemble_info *info)
FIXME: Where does mips_target_info come from? */
target_processor = mips_target_info.processor;
mips_isa = mips_target_info.isa;
mips_ase = mips_target_info.ase;
#else
chosen_arch = choose_arch_by_number (info->mach);
if (chosen_arch != NULL)
{
mips_processor = chosen_arch->processor;
mips_isa = chosen_arch->isa;
mips_ase = chosen_arch->ase;
mips_cp0_names = chosen_arch->cp0_names;
mips_cp0sel_names = chosen_arch->cp0sel_names;
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
@ -827,9 +834,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
if (CONST_STRNEQ (option, "virt"))
{
mips_isa |= INSN_VIRT;
mips_ase |= ASE_VIRT;
if (mips_isa & ISA_MIPS64R2)
mips_isa |= INSN_VIRT64;
mips_ase |= ASE_VIRT64;
return;
}
@ -1514,7 +1521,7 @@ print_insn_mips (bfd_vma memaddr,
const char *d;
/* We always allow to disassemble the jalx instruction. */
if (!opcode_is_member (op, mips_isa, mips_processor)
if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
&& strcmp (op->name, "jalx"))
continue;

1442
opcodes/mips-opc.c
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