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* arm-tdep.c (arm_analyze_prologue): Do not abort parsing when
encountering a load via a non-SP register.
This commit is contained in:
@ -1,3 +1,8 @@
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2011-03-21 Ulrich Weigand <ulrich.weigand@linaro.org>
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* arm-tdep.c (arm_analyze_prologue): Do not abort parsing when
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encountering a load via a non-SP register.
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2011-03-21 Ulrich Weigand <uweigand@de.ibm.com>
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2011-03-21 Ulrich Weigand <uweigand@de.ibm.com>
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* tramp-frame.c (tramp_frame_prepend_unwinder): Set stop_reason
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* tramp-frame.c (tramp_frame_prepend_unwinder): Set stop_reason
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@ -1856,23 +1856,15 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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else if (arm_instruction_changes_pc (insn))
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else if (arm_instruction_changes_pc (insn))
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/* Don't scan past anything that might change control flow. */
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/* Don't scan past anything that might change control flow. */
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break;
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break;
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else if ((insn & 0xfe500000) == 0xe8100000) /* ldm */
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else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */
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{
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&& pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
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/* Ignore block loads from the stack, potentially copying
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/* Ignore block loads from the stack, potentially copying
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parameters from memory. */
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parameters from memory. */
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if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
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continue;
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continue;
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else
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else if ((insn & 0xfc500000) == 0xe4100000
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break;
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&& pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
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}
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else if ((insn & 0xfc500000) == 0xe4100000)
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{
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/* Similarly ignore single loads from the stack. */
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/* Similarly ignore single loads from the stack. */
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if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
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continue;
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continue;
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else
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break;
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}
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else if ((insn & 0xffff0ff0) == 0xe1a00000)
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else if ((insn & 0xffff0ff0) == 0xe1a00000)
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/* MOV Rd, Rm. Skip register copies, i.e. saves to another
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/* MOV Rd, Rm. Skip register copies, i.e. saves to another
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register instead of the stack. */
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register instead of the stack. */
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