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Fix mips SWL on 64bit ISA when 32 bit word appears in second half of

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64 bit bus.
Test.
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Andrew Cagney
1998-05-25 05:48:34 +00:00
parent 21b3bc779c
commit ce82378189
8 changed files with 666 additions and 0 deletions
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sim/mips/ChangeLog
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@ -1,3 +1,10 @@
Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
* mips.igen (do_store_left, do_load_left): Compute nr of left and
right bits and then re-align left hand bytes to correct byte
lanes. Fix incorrect computation in do_store_left when loading
bytes from second word.
start-sanitize-tx3904
Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>