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[binutils][aarch64] New sve_size_013 iclass.

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Add sve_size_013 instruction class

This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_013 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_013 iclass decode.
This commit is contained in:
Matthew Malcomson
2019-05-09 10:29:21 +01:00
parent 3c705960ca
commit cd50a87ae2
5 changed files with 30 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/ChangeLog
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@ -1,3 +1,7 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.

1
include/opcode/aarch64.h
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@ -596,6 +596,7 @@ enum aarch64_insn_class
sve_size_sd, sve_size_sd,
sve_size_bh, sve_size_bh,
sve_size_sd2, sve_size_sd2,
sve_size_013,
testbranch, testbranch,
cryptosm3, cryptosm3,
cryptosm4, cryptosm4,

7
opcodes/ChangeLog
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@ -1,3 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_013 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_013 iclass decode.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle

8
opcodes/aarch64-asm.c
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@ -1613,6 +1613,7 @@ do_special_encoding (struct aarch64_inst *inst)
static void static void
aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
{ {
int variant = 0;
switch (inst->opcode->iclass) switch (inst->opcode->iclass)
{ {
case sve_cpy: case sve_cpy:
@ -1669,6 +1670,13 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
aarch64_get_variant (inst) + 1, 0); aarch64_get_variant (inst) + 1, 0);
break; break;
case sve_size_013:
variant = aarch64_get_variant (inst);
if (variant == 2)
variant = 3;
insert_field (FLD_size, &inst->value, variant, 0);
break;
default: default:
break; break;
} }

10
opcodes/aarch64-dis.c
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@ -2822,6 +2822,16 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = i - 1; variant = i - 1;
break; break;
case sve_size_013:
i = extract_field (FLD_size, inst->value, 0);
if (i == 2)
return FALSE;
if (i == 3)
variant = 2;
else
variant = i;
break;
default: default:
/* No mapping between instruction class and qualifiers. */ /* No mapping between instruction class and qualifiers. */
return TRUE; return TRUE;