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sim: frv: hoist cgen rules to top-level

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This commit is contained in:
Mike Frysinger
2023-01-01 21:18:50 -05:00
parent 3298ee7a2c
commit cd313814aa
3 changed files with 21 additions and 24 deletions
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10
sim/Makefile.in
View File

@ -3606,6 +3606,16 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen: frv/cgen-arch frv/cgen-cpu-decode
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH)
@SIM_ENABLE_ARCH_frv_TRUE@frv/arch.h frv/arch.c frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \

24
sim/frv/Makefile.in
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@ -31,33 +31,9 @@ SIM_OBJS = \
SIM_EXTRA_CFLAGS = @SIM_FRV_TRAPDUMP_FLAGS@
SIM_EXTRA_CLEAN = frv-clean
# Some modules don't build cleanly yet.
memory.o sem.o: SIM_WERROR_CFLAGS =
## COMMON_POST_CONFIG_FRAG
arch = frv
frv-clean:
rm -f tmp-*
rm -f stamp-arch stamp-cpu
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache"
$(SILENCE) touch $@
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
# @true
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"
$(SILENCE) touch $@
cpu.h sem.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
# @true

11
sim/frv/local.mk
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@ -47,3 +47,14 @@ SIM_ALL_RECURSIVE_DEPS += $(%C%_BUILD_OUTPUTS)
$(AM_V_at)touch $@
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
## Target that triggers all cgen targets that works when --disable-cgen-maint.
%D%/cgen: %D%/cgen-arch %D%/cgen-cpu-decode
%D%/cgen-arch:
$(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH)
%D%/arch.h %D%/arch.c %D%/cpuall.h: @CGEN_MAINT@ %D%/cgen-arch
%D%/cgen-cpu-decode:
$(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
%D%/cpu.h %D%/sem.c %D%/model.c %D%/decode.c %D%/decode.h: @CGEN_MAINT@ %D%/cgen-cpu-decode