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MIPS/opcodes: Free up redundant `g' operand code

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In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.

Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.

Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
	and "mtthc2" to using the `G' rather than `g' operand code for
	the coprocessor control register referred.

	include/
	* opcode/mips.h: Complement change made to opcodes and remove
	references to the `g' regular MIPS ISA operand code.
This commit is contained in:
Maciej W. Rozycki
2021-05-29 03:26:32 +02:00
parent c9de3168a9
commit cccc84faff
4 changed files with 15 additions and 6 deletions
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3
include/opcode/mips.h
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@ -899,7 +899,6 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
MCU ASE usage:
@ -1001,7 +1000,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
"1234567890"
"%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
"abcdef hijkl opqrstuvwx z"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more: