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RISC-V: Add support for XCVmac extension in CV32E40P

Browse Source 
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
	* testsuite/gas/riscv/cv-mac-insns.d: New test.
	* testsuite/gas/riscv/cv-mac-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble information with
          the EXTRACT macro implemented.
	* riscv-opc.c: Defined the MASK and added
          XCVmac instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCVmac.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for uimm.
	(enum riscv_insn_class): Added the XCVmac instruction class.
This commit is contained in:
Mary Bennett
2023-10-02 03:02:05 +01:00
committed by Nelson Chu
parent cf0d07fd07
commit ccb388ca39
15 changed files with 643 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
include/opcode/riscv-opc.h
View File

@@ -2320,6 +2320,43 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
#define MATCH_CV_MSU 0x9200302b
#define MASK_CV_MSU 0xfe00707f
#define MATCH_CV_MULSN 0x405b
#define MASK_CV_MULSN 0xc000707f
#define MATCH_CV_MULHHSN 0x4000405b
#define MASK_CV_MULHHSN 0xc000707f
#define MATCH_CV_MULSRN 0x8000405b
#define MASK_CV_MULSRN 0xc000707f
#define MATCH_CV_MULHHSRN 0xc000405b
#define MASK_CV_MULHHSRN 0xc000707f
#define MATCH_CV_MULUN 0x505b
#define MASK_CV_MULUN 0xc000707f
#define MATCH_CV_MULHHUN 0x4000505b
#define MASK_CV_MULHHUN 0xc000707f
#define MATCH_CV_MULURN 0x8000505b
#define MASK_CV_MULURN 0xc000707f
#define MATCH_CV_MULHHURN 0xc000505b
#define MASK_CV_MULHHURN 0xc000707f
#define MATCH_CV_MACSN 0x605b
#define MASK_CV_MACSN 0xc000707f
#define MATCH_CV_MACHHSN 0x4000605b
#define MASK_CV_MACHHSN 0xc000707f
#define MATCH_CV_MACSRN 0x8000605b
#define MASK_CV_MACSRN 0xc000707f
#define MATCH_CV_MACHHSRN 0xc000605b
#define MASK_CV_MACHHSRN 0xc000707f
#define MATCH_CV_MACUN 0x705b
#define MASK_CV_MACUN 0xc000707f
#define MATCH_CV_MACHHUN 0x4000705b
#define MASK_CV_MACHHUN 0xc000707f
#define MATCH_CV_MACURN 0x8000705b
#define MASK_CV_MACURN 0xc000707f
#define MATCH_CV_MACHHURN 0xc000705b
#define MASK_CV_MACHHURN 0xc000707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f

7
include/opcode/riscv.h
View File

@@ -112,6 +112,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)
/* Vendor-specific (CORE-V) extract macros. */
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@@ -163,6 +166,9 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)
/* Vendor-specific (CORE-V) encode macros. */
#define ENCODE_CV_IS3_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -443,6 +449,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,