espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-26 05:47:26 +08:00
Code Issues Packages Projects Releases Wiki Activity

ubsan: m32r: left shift of negative value

Browse Source 
cpu/
	* m32r.cpu (f-disp8): Avoid left shift of negative values.
	(f-disp16, f-disp24): Likewise.
opcodes/
	* m32r-ibld.c: Regenerate.
This commit is contained in:
Alan Modra
2020-01-04 08:11:43 +10:30
parent 5f57d4ecf5
commit c9ae58fe32
4 changed files with 15 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
cpu/ChangeLog
View File

@ -1,3 +1,8 @@
2020-02-04 Alan Modra <amodra@gmail.com>
* m32r.cpu (f-disp8): Avoid left shift of negative values.
(f-disp16, f-disp24): Likewise.
2019-12-23 Alan Modra <amodra@gmail.com> 2019-12-23 Alan Modra <amodra@gmail.com>
* iq2000.cpu (f-offset): Avoid left shift of negative values. * iq2000.cpu (f-offset): Avoid left shift of negative values.

6
cpu/m32r.cpu
View File

@ -478,13 +478,13 @@
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
(df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT (df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) ((value pc) (add WI (mul WI value (const 4)) (and WI pc (const -4)))))
(df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT (df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT
((value pc) (sra WI (sub WI value pc) (const 2))) ((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc))) ((value pc) (add WI (mul WI value (const 4)) pc)))
(df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT (df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT
((value pc) (sra WI (sub WI value pc) (const 2))) ((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc))) ((value pc) (add WI (mul WI value (const 4)) pc)))
(dnf f-op23 "op2.3" () 9 3) (dnf f-op23 "op2.3" () 9 3)
(dnf f-op3 "op3" () 14 2) (dnf f-op3 "op3" () 14 2)

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2020-01-04 Alan Modra <amodra@gmail.com>
* m32r-ibld.c: Regenerate.
2020-01-04 Alan Modra <amodra@gmail.com> 2020-01-04 Alan Modra <amodra@gmail.com>
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

6
opcodes/m32r-ibld.c
View File

@ -723,7 +723,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
{ {
long value; long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc)); value = ((((value) * (4))) + (pc));
fields->f_disp16 = value; fields->f_disp16 = value;
} }
break; break;
@ -731,7 +731,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
{ {
long value; long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value); length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc)); value = ((((value) * (4))) + (pc));
fields->f_disp24 = value; fields->f_disp24 = value;
} }
break; break;
@ -739,7 +739,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
{ {
long value; long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value); length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
value = ((((value) << (2))) + (((pc) & (-4)))); value = ((((value) * (4))) + (((pc) & (-4))));
fields->f_disp8 = value; fields->f_disp8 = value;
} }
break; break;