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Initial creation of sourceware repository
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Stan Shebs
234
sim/igen/igen.h
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234
sim/igen/igen.h
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/* This file is part of the program psim.
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Copyright (C) 1994-1998, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* code-generation options: */
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typedef enum {
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/* Transfer control to an instructions semantic code using the the
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standard call/return mechanism */
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generate_calls,
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/* Transfer control to an instructions semantic code using
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(computed) goto's instead of the more conventional call/return
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mechanism */
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generate_jumps,
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} igen_code;
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typedef enum {
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nia_is_cia_plus_one,
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nia_is_void,
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nia_is_invalid,
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} igen_nia;
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typedef struct _igen_gen_options igen_gen_options;
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struct _igen_gen_options {
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int direct_access;
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int semantic_icache;
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int insn_in_icache;
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int conditional_issue;
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int slot_verification;
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int delayed_branch;
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/* If zeroing a register, which one? */
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int zero_reg;
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int zero_reg_nr;
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/* should multiple simulators be generated? */
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int multi_sim;
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/* name of the default multi-sim model */
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char *default_model;
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/* should the simulator support multi word instructions and if so,
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what is the max nr of words. */
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int multi_word;
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/* SMP? Should the generated code include SMP support (>0) and if
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so, for how many processors? */
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int smp;
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/* how should the next instruction address be computed? */
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igen_nia nia;
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/* nr of instructions in the decoded instruction cache */
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int icache;
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int icache_size;
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/* see above */
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igen_code code;
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};
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typedef struct _igen_trace_options igen_trace_options;
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struct _igen_trace_options {
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int rule_selection;
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int rule_rejection;
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int insn_insertion;
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int insn_expansion;
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int entries;
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int combine;
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};
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typedef struct _igen_name {
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char *u;
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char *l;
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} igen_name;
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typedef struct _igen_module {
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igen_name prefix;
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igen_name suffix;
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} igen_module;
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typedef struct _igen_module_options {
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igen_module global;
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igen_module engine;
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igen_module icache;
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igen_module idecode;
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igen_module itable;
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igen_module semantics;
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igen_module support;
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} igen_module_options;
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typedef struct _igen_decode_options igen_decode_options ;
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struct _igen_decode_options {
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/* Combine tables? Should the generator make a second pass through
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each generated table looking for any sub-entries that contain the
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same instructions. Those entries being merged into a single
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table */
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int combine;
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/* Instruction expansion? Should the semantic code for each
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instruction, when the oportunity arrises, be expanded according
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to the variable opcode files that the instruction decode process
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renders constant */
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int duplicate;
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/* Treat reserved fields as constant (zero) instead of ignoring
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their value when determining decode tables */
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int zero_reserved;
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/* Convert any padded switch rules into goto_switch */
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int switch_as_goto;
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/* Force all tables to be generated with this lookup mechanism */
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char *overriding_gen;
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};
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typedef struct _igen_warn_options igen_warn_options;
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struct _igen_warn_options {
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/* Issue warning about discarded instructions */
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int discard;
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/* Issue warning about invalid instruction widths */
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int width;
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/* Issue warning about unimplemented instructions */
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int unimplemented;
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};
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typedef struct _igen_options igen_options;
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struct _igen_options {
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/* What does the instruction look like - bit ordering, size, widths or
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offesets */
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int hi_bit_nr;
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int insn_bit_size;
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int insn_specifying_widths;
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/* what should global names be prefixed with? */
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igen_module_options module;
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/* See above for options and flags */
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igen_gen_options gen;
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/* See above for trace options */
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igen_trace_options trace;
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/* See above for include options */
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table_include *include;
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/* See above for decode options */
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igen_decode_options decode;
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/* Filter set to be used on the flag field of the instruction table */
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filter *flags_filter;
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/* See above for warn options */
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igen_warn_options warn;
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/* Be more picky about the input */
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error_func (*warning);
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/* Model (processor) set - like flags_filter. Used to select the
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specific ISA within a processor family. */
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filter *model_filter;
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/* Format name set */
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filter *format_name_filter;
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};
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extern igen_options options;
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/* default options - hopefully backward compatible */ \
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#define INIT_OPTIONS() \
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do { \
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memset (&options, 0, sizeof options); \
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memset (&options.warn, -1, sizeof (options.warn)); \
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options.hi_bit_nr = 0; \
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options.insn_bit_size = default_insn_bit_size; \
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options.insn_specifying_widths = 0; \
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options.module.global.prefix.u = ""; \
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options.module.global.prefix.l = ""; \
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/* the prefixes */ \
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options.module.engine = options.module.global; \
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options.module.icache = options.module.global; \
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options.module.idecode = options.module.global; \
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options.module.itable = options.module.global; \
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options.module.semantics = options.module.global; \
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options.module.support = options.module.global; \
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/* the suffixes */ \
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options.module.engine.suffix.l = "engine"; \
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options.module.engine.suffix.u = "ENGINE"; \
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options.module.icache.suffix.l = "icache"; \
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options.module.icache.suffix.u = "ICACHE"; \
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options.module.idecode.suffix.l = "idecode"; \
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options.module.idecode.suffix.u = "IDECODE"; \
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options.module.itable.suffix.l = "itable"; \
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options.module.itable.suffix.u = "ITABLE"; \
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options.module.semantics.suffix.l = "semantics"; \
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options.module.semantics.suffix.u = "SEMANTICS"; \
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options.module.support.suffix.l = "support"; \
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options.module.support.suffix.u = "SUPPORT"; \
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/* misc stuff */ \
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options.gen.code = generate_calls; \
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options.gen.icache_size = 1024; \
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options.warning = warning; \
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} while (0)
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