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opcodes/arc: Add more nps instructions

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Add dctcp, dcip, dcet, and dcacl instructions.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-4.d: New file.
	* testsuite/gas/arc/nps400-4.s: New file.
	* testsuite/gas/arc/nps400-5.d: New file.
	* testsuite/gas/arc/nps400-5.s: New file.

include/ChangeLog:

	* opcode/arc.h (insn_class_t): Add NET and ACL class.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
This commit is contained in:
Andrew Burgess
2016-03-31 19:51:14 +01:00
parent ee2915c993
commit c8f785f220
9 changed files with 74 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
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@ -1,3 +1,10 @@
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* testsuite/gas/arc/nps400-4.d: New file.
* testsuite/gas/arc/nps400-4.s: New file.
* testsuite/gas/arc/nps400-5.d: New file.
* testsuite/gas/arc/nps400-5.s: New file.
2016-04-19 Martin Galvan <martin.galvan@tallertechnologies.com>
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve

12
gas/testsuite/gas/arc/nps400-4.d Normal file
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@ -0,0 +1,12 @@
#as: -mcpu=nps400
#objdump: -dr
.*: +file format .*arc.*
Disassembly of section .text:
[0-9a-f]+ <.*>:
0: 3a2f 1300 dctcp r10,r12
4: 3e29 13cd dcip r13,r14,r15
8: 382f 2442 dcet r16,r17
c: 3b20 2512 dcet r18,r19,r20

11
gas/testsuite/gas/arc/nps400-4.s Normal file
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@ -0,0 +1,11 @@
.text
/* dctcp */
dctcp r10, r12
/* dcip */
dcip r13, r14, r15
/* dcet */
dcet r16, r17
dcet r18, r19, r20

10
gas/testsuite/gas/arc/nps400-5.d Normal file
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@ -0,0 +1,10 @@
#as: -mcpu=nps400
#objdump: -dr
.*: +file format .*arc.*
Disassembly of section .text:
[0-9a-f]+ <.*>:
0: 3925 0080 dcacl r0,r1,r2
4: 3c25 8143 dcacl.f r3,r4,r5

5
gas/testsuite/gas/arc/nps400-5.s Normal file
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@ -0,0 +1,5 @@
.text
/* dcacl */
dcacl r0, r1, r2
dcacl.f r3, r4, r5

4
include/ChangeLog
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@ -1,3 +1,7 @@
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* opcode/arc.h (insn_class_t): Add NET and ACL class.
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.

2
include/opcode/arc.h
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@ -47,6 +47,8 @@ typedef enum
LOGICAL,
MEMORY,
BITOP,
NET,
ACL,
} insn_class_t;
/* Instruction Subclass. */

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.in: Regenerated with automake 1.11.6.

19
opcodes/arc-nps400-tbl.h
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@ -124,6 +124,25 @@
/* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */
{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
/**** Protocol Decoder Instructions ****/
/* dctcp b,c 00111bbb001011110bbbcccccc000000 */
{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
/* dcip a,b,c 00111bbb001011110bbbccccccaaaaaa */
{ "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
/* dcet b,c 00111bbb001011110bbbcccccc000010 */
{ "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
/* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */
{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
/**** ACL Instructions ****/
/* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */
{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_NPS400, ACL, NONE, { RA, RB, RC }, { C_F }},
/**** Pipeline Control Instructions ****/
/* schd<.rw|.rd> */