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[AArch64] Add ARMv8.3 PACGA instruction

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Add support for the ARMv8.3 PACGA instruction.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (arch64_opcode_table): Add pacga.
	(AARCH64_OPERANDS): Add Rm_SP.
	* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/pac.s: Add pacga.
	* testsuite/gas/aarch64/pac.d: Add pacga.
This commit is contained in:
Szabolcs Nagy
2016-11-11 10:39:46 +00:00
parent a2cfc830e7
commit c84364ece4
12 changed files with 2025 additions and 1979 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/pac.s: Add pacga.
* testsuite/gas/aarch64/pac.d: Add pacga.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/pac.s: New. * testsuite/gas/aarch64/pac.s: New.

2
gas/config/tc-aarch64.c
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@ -4983,6 +4983,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP: case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_Rm_SP:
case AARCH64_OPND_Fd: case AARCH64_OPND_Fd:
case AARCH64_OPND_Fn: case AARCH64_OPND_Fn:
case AARCH64_OPND_Fm: case AARCH64_OPND_Fm:
@ -5314,6 +5315,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP: case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_SVE_Rn_SP: case AARCH64_OPND_SVE_Rn_SP:
case AARCH64_OPND_Rm_SP:
po_int_reg_or_fail (REG_TYPE_R_SP); po_int_reg_or_fail (REG_TYPE_R_SP);
break; break;

2
gas/testsuite/gas/aarch64/pac.d
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@ -32,3 +32,5 @@ Disassembly of section \.text:
5c: dac13fe5 autdzb x5 5c: dac13fe5 autdzb x5
60: dac143e5 xpaci x5 60: dac143e5 xpaci x5
64: dac147e5 xpacd x5 64: dac147e5 xpacd x5
68: 9ac33041 pacga x1, x2, x3
6c: 9adf3041 pacga x1, x2, sp

3
gas/testsuite/gas/aarch64/pac.s
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@ -32,3 +32,6 @@
xpaci x5 xpaci x5
xpacd x5 xpacd x5
pacga x1, x2, x3
pacga x1, x2, sp

4
include/ChangeLog
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@ -1,3 +1,7 @@
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define. * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.

1
include/opcode/aarch64.h
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@ -140,6 +140,7 @@ enum aarch64_opnd
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_PAIRREG, /* Paired register operand. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */

9
opcodes/ChangeLog
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@ -1,3 +1,12 @@
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add pacga.
(AARCH64_OPERANDS): Add Rm_SP.
* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia, * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,

815
opcodes/aarch64-asm-2.c
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File diff suppressed because it is too large Load Diff

3104
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

53
opcodes/aarch64-opc-2.c
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@ -35,6 +35,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"},
{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"}, {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"}, {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"}, {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
@ -208,48 +209,48 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] = static const unsigned op_enum_table [] =
{ {
0, 0,
846,
847, 847,
848, 848,
851, 849,
852, 852,
853, 853,
854, 854,
855, 855,
849,
850,
856, 856,
850,
851,
857, 857,
879, 858,
880, 880,
881, 881,
884, 882,
885, 885,
886, 886,
887, 887,
888, 888,
882,
883,
889, 889,
883,
884,
890, 890,
933, 891,
934, 934,
935, 935,
936, 936,
937,
12, 12,
627, 627,
628, 628,
1128,
1130,
1132,
940,
1131,
1129, 1129,
1131,
1133,
941,
1132,
1130,
311, 311,
615, 615,
626, 626,
625, 625,
938, 939,
622, 622,
619, 619,
611, 611,
@ -259,34 +260,34 @@ static const unsigned op_enum_table [] =
621, 621,
623, 623,
624, 624,
948, 949,
643, 643,
646, 646,
649, 649,
644, 644,
647, 647,
790, 791,
171, 171,
172, 172,
173, 173,
174, 174,
507, 507,
731, 732,
380, 380,
382, 382,
404, 404,
406, 406,
1193,
1198,
1191,
1190,
1194, 1194,
1201, 1199,
1203, 1192,
1191,
1195,
1202,
1204, 1204,
1200,
1206,
1205, 1205,
1201,
1207,
1206,
}; };
/* Given the opcode enumerator OP, return the pointer to the corresponding /* Given the opcode enumerator OP, return the pointer to the corresponding

1
opcodes/aarch64-opc.c
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@ -2989,6 +2989,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP: case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_SVE_Rn_SP: case AARCH64_OPND_SVE_Rn_SP:
case AARCH64_OPND_Rm_SP:
assert (opnd->qualifier == AARCH64_OPND_QLF_W assert (opnd->qualifier == AARCH64_OPND_QLF_W
|| opnd->qualifier == AARCH64_OPND_QLF_WSP || opnd->qualifier == AARCH64_OPND_QLF_WSP
|| opnd->qualifier == AARCH64_OPND_QLF_X || opnd->qualifier == AARCH64_OPND_QLF_X

3
opcodes/aarch64-tbl.h
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@ -2694,6 +2694,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
/* CRC instructions. */ /* CRC instructions. */
_CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
_CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
@ -3987,6 +3988,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"an integer or stack pointer register") \ "an integer or stack pointer register") \
Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
"an integer or stack pointer register") \ "an integer or stack pointer register") \
Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \
"an integer or stack pointer register") \
X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
"the second reg of a pair") \ "the second reg of a pair") \
Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \