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Support AVX Programming Reference (June, 2010)
gas/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd and .f16c. * doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c. gas/testsuite/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/arch-10.s: Add xsaveopt. * gas/i386/x86-64-arch-2.s: Likwise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/f16c-intel.d: New. * gas/i386/f16c.d: Likewise. * gas/i386/f16c.s: Likewise. * gas/i386/fsgs-intel.d: Likewise. * gas/i386/fsgs.d: Likewise. * gas/i386/fsgs.s: Likewise. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/rdrnd.s: Likewise. * gas/i386/x86-64-f16c-intel.d: Likewise. * gas/i386/x86-64-f16c.d: Likewise. * gas/i386/x86-64-f16c.s: Likewise. * gas/i386/x86-64-fsgs-intel.d: Likewise. * gas/i386/x86-64-fsgs.d: Likewise. * gas/i386/x86-64-fsgs.s: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. * gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel, rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs, x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel. * gas/i386/x86-64-xsave.s: Add tests for xsaveopt64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (PREFIX_0FAE_REG_0): New. (PREFIX_0FAE_REG_1): Likewise. (PREFIX_0FAE_REG_2): Likewise. (PREFIX_0FAE_REG_3): Likewise. (PREFIX_VEX_3813): Likewise. (PREFIX_VEX_3A1D): Likewise. (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. * i386-opc.h (CpuXsaveopt): New. (CpuFSGSBase):Likewise. (CpuRdRnd): Likewise. (CpuF16C): Likewise. (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and cpuf16c. * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
This commit is contained in:
H.J. Lu
@ -1,3 +1,33 @@
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2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2010)
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* i386-dis.c (PREFIX_0FAE_REG_0): New.
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(PREFIX_0FAE_REG_1): Likewise.
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(PREFIX_0FAE_REG_2): Likewise.
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(PREFIX_0FAE_REG_3): Likewise.
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(PREFIX_VEX_3813): Likewise.
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(PREFIX_VEX_3A1D): Likewise.
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(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
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PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
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PREFIX_VEX_3A1D.
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(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
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(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
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PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
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* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
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CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
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(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
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* i386-opc.h (CpuXsaveopt): New.
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(CpuFSGSBase):Likewise.
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(CpuRdRnd): Likewise.
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(CpuF16C): Likewise.
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(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
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cpuf16c.
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* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
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wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
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2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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* ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
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@ -741,6 +741,10 @@ enum
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PREFIX_0F7D,
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PREFIX_0F7E,
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PREFIX_0F7F,
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PREFIX_0FAE_REG_0,
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PREFIX_0FAE_REG_1,
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PREFIX_0FAE_REG_2,
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PREFIX_0FAE_REG_3,
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PREFIX_0FB8,
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PREFIX_0FBD,
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PREFIX_0FC2,
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@ -936,6 +940,7 @@ enum
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PREFIX_VEX_380D,
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PREFIX_VEX_380E,
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PREFIX_VEX_380F,
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PREFIX_VEX_3813,
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PREFIX_VEX_3817,
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PREFIX_VEX_3818,
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PREFIX_VEX_3819,
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@ -1026,6 +1031,7 @@ enum
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PREFIX_VEX_3A17,
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PREFIX_VEX_3A18,
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PREFIX_VEX_3A19,
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PREFIX_VEX_3A1D,
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PREFIX_VEX_3A20,
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PREFIX_VEX_3A21,
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PREFIX_VEX_3A22,
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@ -3033,6 +3039,30 @@ static const struct dis386 prefix_table[][4] = {
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{ "movdqa", { EXxS, XM } },
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},
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/* PREFIX_0FAE_REG_0 */
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{
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{ Bad_Opcode },
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{ "rdfsbase", { Ev } },
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},
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/* PREFIX_0FAE_REG_1 */
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{
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{ Bad_Opcode },
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{ "rdgsbase", { Ev } },
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},
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/* PREFIX_0FAE_REG_2 */
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{
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{ Bad_Opcode },
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{ "wrfsbase", { Ev } },
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},
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/* PREFIX_0FAE_REG_3 */
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{
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{ Bad_Opcode },
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{ "wrgsbase", { Ev } },
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},
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/* PREFIX_0FB8 */
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{
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{ Bad_Opcode },
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@ -4419,6 +4449,13 @@ static const struct dis386 prefix_table[][4] = {
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{ VEX_W_TABLE (VEX_W_380F_P_2) },
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},
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/* PREFIX_VEX_3813 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vcvtph2ps", { XM, EXxmmq } },
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},
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/* PREFIX_VEX_3817 */
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{
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{ Bad_Opcode },
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@ -5050,6 +5087,13 @@ static const struct dis386 prefix_table[][4] = {
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{ VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
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},
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/* PREFIX_VEX_3A1D */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vcvtps2ph", { EXxmmq, XM, Ib } },
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},
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/* PREFIX_VEX_3A20 */
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{
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{ Bad_Opcode },
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@ -7533,7 +7577,7 @@ static const struct dis386 vex_table[][256] = {
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_3813) },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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@ -7835,7 +7879,7 @@ static const struct dis386 vex_table[][256] = {
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_3A1D) },
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{ Bad_Opcode },
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{ Bad_Opcode },
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/* 20 */
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@ -10355,18 +10399,22 @@ static const struct dis386 mod_table[][2] = {
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{
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/* MOD_0FAE_REG_0 */
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{ "fxsave", { FXSAVE } },
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{ PREFIX_TABLE (PREFIX_0FAE_REG_0) },
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},
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{
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/* MOD_0FAE_REG_1 */
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{ "fxrstor", { FXSAVE } },
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{ PREFIX_TABLE (PREFIX_0FAE_REG_1) },
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},
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{
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/* MOD_0FAE_REG_2 */
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{ "ldmxcsr", { Md } },
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{ PREFIX_TABLE (PREFIX_0FAE_REG_2) },
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},
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{
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/* MOD_0FAE_REG_3 */
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{ "stmxcsr", { Md } },
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{ PREFIX_TABLE (PREFIX_0FAE_REG_3) },
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},
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{
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/* MOD_0FAE_REG_4 */
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@ -10379,7 +10427,7 @@ static const struct dis386 mod_table[][2] = {
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},
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{
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/* MOD_0FAE_REG_6 */
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{ Bad_Opcode },
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{ "xsaveopt", { FXSAVE } },
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{ RM_TABLE (RM_0FAE_REG_6) },
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},
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{
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@ -10402,6 +10450,7 @@ static const struct dis386 mod_table[][2] = {
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{
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/* MOD_0FC7_REG_6 */
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{ PREFIX_TABLE (PREFIX_0FC7_REG_6) },
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{ "rdrnd", { Ev } },
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},
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{
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/* MOD_0FC7_REG_7 */
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@ -122,6 +122,8 @@ static initializer cpu_flag_init[] =
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"CpuSMX" },
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{ "CPU_XSAVE_FLAGS",
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"CpuXsave" },
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{ "CPU_XSAVEOPT_FLAGS",
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"CpuXsaveopt" },
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{ "CPU_AES_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
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{ "CPU_PCLMUL_FLAGS",
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@ -140,6 +142,12 @@ static initializer cpu_flag_init[] =
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"CpuRdtscp" },
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{ "CPU_EPT_FLAGS",
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"CpuEPT" },
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{ "CPU_FSGSBASE_FLAGS",
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"CpuFSGSBase" },
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{ "CPU_RDRND_FLAGS",
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"CpuRdRnd" },
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{ "CPU_F16C_FLAGS",
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"CpuF16C" },
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{ "CPU_3DNOW_FLAGS",
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"CpuMMX|Cpu3dnow" },
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{ "CPU_3DNOWA_FLAGS",
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@ -300,6 +308,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuSMX),
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BITFIELD (CpuABM),
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BITFIELD (CpuXsave),
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BITFIELD (CpuXsaveopt),
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BITFIELD (CpuAES),
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BITFIELD (CpuPCLMUL),
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BITFIELD (CpuFMA),
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@ -310,6 +319,9 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuMovbe),
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BITFIELD (CpuEPT),
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BITFIELD (CpuRdtscp),
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BITFIELD (CpuFSGSBase),
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BITFIELD (CpuRdRnd),
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BITFIELD (CpuF16C),
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BITFIELD (Cpu64),
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BITFIELD (CpuNo64),
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#ifdef CpuUnused
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@ -22,292 +22,312 @@
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#define CPU_UNKNOWN_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 0, 1, 1 } }
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1, 1, 1, 1, 1, 0, 1, 1 } }
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#define CPU_GENERIC32_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_GENERIC64_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 0, 0, 0 } }
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0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_NONE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I186_FLAGS \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I286_FLAGS \
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{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I386_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I486_FLAGS \
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{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I586_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I686_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P3_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P4_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NOCONA_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 0, 0, 0 } }
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0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_CORE_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_CORE2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 0, 0, 0 } }
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0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_COREI7_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
|
||||
1, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -94,6 +94,8 @@ enum
|
||||
CpuL1OM,
|
||||
/* Xsave/xrstor New Instuctions support required */
|
||||
CpuXsave,
|
||||
/* Xsaveopt New Instuctions support required */
|
||||
CpuXsaveopt,
|
||||
/* AES support required */
|
||||
CpuAES,
|
||||
/* PCLMUL support required */
|
||||
@ -112,6 +114,12 @@ enum
|
||||
CpuEPT,
|
||||
/* RDTSCP Instuction support required */
|
||||
CpuRdtscp,
|
||||
/* FSBSBASE Instructions required */
|
||||
CpuFSGSBase,
|
||||
/* RDRND Instructions required */
|
||||
CpuRdRnd,
|
||||
/* F16C Instructions required */
|
||||
CpuF16C,
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
CpuLM,
|
||||
/* 64bit support required */
|
||||
@ -168,6 +176,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpuavx:1;
|
||||
unsigned int cpul1om:1;
|
||||
unsigned int cpuxsave:1;
|
||||
unsigned int cpuxsaveopt:1;
|
||||
unsigned int cpuaes:1;
|
||||
unsigned int cpupclmul:1;
|
||||
unsigned int cpufma:1;
|
||||
@ -177,6 +186,9 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
unsigned int cpurdtscp:1;
|
||||
unsigned int cpufsgsbase:1;
|
||||
unsigned int cpurdrnd:1;
|
||||
unsigned int cpuf16c:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
|
||||
@ -1754,6 +1754,10 @@ xrstor64, 1, 0xfae, 0x5, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu
|
||||
xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
|
||||
// xsaveopt
|
||||
xsaveopt, 1, 0xfae, 0x6, 2, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xsaveopt64, 1, 0xfae, 0x6, 2, CpuXsaveopt|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// AES instructions.
|
||||
|
||||
aesdec, 2, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
@ -2386,6 +2390,18 @@ vpclmulhqlqdq, 3, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVV
|
||||
vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// FSGSBASE, RDRND and F16C
|
||||
|
||||
rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdrnd, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
|
||||
wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM }
|
||||
vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
|
||||
// FMA instructions
|
||||
|
||||
vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
5760
opcodes/i386-tbl.h
5760
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user