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2000-08-30 Kazu Hirata <kazu@hxi.com>

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* tic80-dis.c: Fix formatting.
This commit is contained in:
Kazu Hirata
2000-08-30 18:51:25 +00:00
parent 7ee3806531
commit c6d805e091
2 changed files with 71 additions and 77 deletions
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4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2000-08-30 Kazu Hirata <kazu@hxi.com>
* tic80-dis.c: Fix formatting.
2000-08-29 Kazu Hirata <kazu@hxi.com> 2000-08-29 Kazu Hirata <kazu@hxi.com>
* w65-dis.c: Fix formatting. * w65-dis.c: Fix formatting.

24
opcodes/tic80-dis.c
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@ -1,5 +1,5 @@
/* Print TI TMS320C80 (MVP) instructions /* Print TI TMS320C80 (MVP) instructions
Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc. Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by
@ -36,7 +36,6 @@ static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsign
const struct tic80_opcode *)); const struct tic80_opcode *));
static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma, static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
unsigned long *)); unsigned long *));
/* Print an integer operand. Try to be somewhat smart about the /* Print an integer operand. Try to be somewhat smart about the
format by assuming that small positive or negative integers are format by assuming that small positive or negative integers are
@ -58,7 +57,6 @@ print_operand_integer (info, value)
(*info->fprintf_func) (info->stream, "%ld", value); (*info->fprintf_func) (info->stream, "%ld", value);
} }
} }
/* FIXME: depends upon sizeof (long) == sizeof (float) and /* FIXME: depends upon sizeof (long) == sizeof (float) and
also upon host floating point format matching target also upon host floating point format matching target
@ -74,7 +72,6 @@ print_operand_float (info, value)
fval.l = value; fval.l = value;
(*info->fprintf_func) (info->stream, "%g", fval.f); (*info->fprintf_func) (info->stream, "%g", fval.f);
} }
static void static void
print_operand_control_register (info, value) print_operand_control_register (info, value)
@ -93,7 +90,6 @@ print_operand_control_register (info, value)
(*info->fprintf_func) (info->stream, "%#lx", value); (*info->fprintf_func) (info->stream, "%#lx", value);
} }
} }
static void static void
print_operand_condition_code (info, value) print_operand_condition_code (info, value)
@ -112,7 +108,6 @@ print_operand_condition_code (info, value)
(*info->fprintf_func) (info->stream, "%ld", value); (*info->fprintf_func) (info->stream, "%ld", value);
} }
} }
static void static void
print_operand_bitnum (info, value) print_operand_bitnum (info, value)
@ -133,7 +128,6 @@ print_operand_bitnum (info, value)
(*info->fprintf_func) (info->stream, "%ld", bitnum); (*info->fprintf_func) (info->stream, "%ld", bitnum);
} }
} }
/* Print the operand as directed by the flags. */ /* Print the operand as directed by the flags. */
@ -194,16 +188,15 @@ print_operand (info, value, insn, operand, memaddr)
print_operand_integer (info, value); print_operand_integer (info, value);
} }
/* If this is a scaled operand, then print the modifier */ /* If this is a scaled operand, then print the modifier. */
if (R_SCALED (insn, operand)) if (R_SCALED (insn, operand))
{ {
(*info->fprintf_func) (info->stream, ":s"); (*info->fprintf_func) (info->stream, ":s");
} }
} }
/* We have chosen an opcode table entry */ /* We have chosen an opcode table entry. */
static int static int
print_one_instruction (info, memaddr, insn, opcode) print_one_instruction (info, memaddr, insn, opcode)
@ -277,14 +270,12 @@ print_one_instruction (info, memaddr, insn, opcode)
} }
return (length); return (length);
} }
/* There are no specific bits that tell us for certain whether a vector /* There are no specific bits that tell us for certain whether a vector
instruction opcode contains one or two instructions. However since instruction opcode contains one or two instructions. However since
a destination register of r0 is illegal, we can check for nonzero a destination register of r0 is illegal, we can check for nonzero
values in both destination register fields. Only opcodes that have values in both destination register fields. Only opcodes that have
two valid instructions will have non-zero in both */ two valid instructions will have non-zero in both. */
#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) #define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
@ -316,7 +307,7 @@ print_instruction (info, memaddr, insn, vec_opcode)
if (opcode == opcode_end) if (opcode == opcode_end)
{ {
/* No match found, just print the bits as a .word directive */ /* No match found, just print the bits as a .word directive. */
(*info->fprintf_func) (info->stream, ".word %#08lx", insn); (*info->fprintf_func) (info->stream, ".word %#08lx", insn);
} }
else else
@ -348,7 +339,7 @@ fill_instruction (info, memaddr, insnp)
bfd_byte buffer[4]; bfd_byte buffer[4];
int status; int status;
/* Get the bits for the next 32 bit word and put in buffer */ /* Get the bits for the next 32 bit word and put in buffer. */
status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
if (status != 0) if (status != 0)
@ -371,12 +362,11 @@ fill_instruction (info, memaddr, insnp)
} }
else else
{ {
/* FIXME: Should probably just default to one or the other */ /* FIXME: Should probably just default to one or the other. */
abort (); abort ();
} }
return (0); return (0);
} }
int int
print_insn_tic80 (memaddr, info) print_insn_tic80 (memaddr, info)