mirror of
https://github.com/espressif/binutils-gdb.git
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2000-08-30 Kazu Hirata <kazu@hxi.com>
* tic80-dis.c: Fix formatting.
This commit is contained in:
@ -1,3 +1,7 @@
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2000-08-30 Kazu Hirata <kazu@hxi.com>
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* tic80-dis.c: Fix formatting.
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2000-08-29 Kazu Hirata <kazu@hxi.com>
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2000-08-29 Kazu Hirata <kazu@hxi.com>
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* w65-dis.c: Fix formatting.
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* w65-dis.c: Fix formatting.
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@ -1,5 +1,5 @@
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/* Print TI TMS320C80 (MVP) instructions
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/* Print TI TMS320C80 (MVP) instructions
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Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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@ -36,7 +36,6 @@ static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsign
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const struct tic80_opcode *));
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const struct tic80_opcode *));
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static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
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static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
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unsigned long *));
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unsigned long *));
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/* Print an integer operand. Try to be somewhat smart about the
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/* Print an integer operand. Try to be somewhat smart about the
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format by assuming that small positive or negative integers are
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format by assuming that small positive or negative integers are
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@ -58,7 +57,6 @@ print_operand_integer (info, value)
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(*info->fprintf_func) (info->stream, "%ld", value);
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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}
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}
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}
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/* FIXME: depends upon sizeof (long) == sizeof (float) and
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/* FIXME: depends upon sizeof (long) == sizeof (float) and
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also upon host floating point format matching target
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also upon host floating point format matching target
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@ -74,7 +72,6 @@ print_operand_float (info, value)
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fval.l = value;
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fval.l = value;
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(*info->fprintf_func) (info->stream, "%g", fval.f);
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(*info->fprintf_func) (info->stream, "%g", fval.f);
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}
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}
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static void
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static void
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print_operand_control_register (info, value)
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print_operand_control_register (info, value)
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@ -93,7 +90,6 @@ print_operand_control_register (info, value)
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(*info->fprintf_func) (info->stream, "%#lx", value);
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(*info->fprintf_func) (info->stream, "%#lx", value);
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}
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}
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}
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}
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static void
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static void
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print_operand_condition_code (info, value)
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print_operand_condition_code (info, value)
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@ -112,7 +108,6 @@ print_operand_condition_code (info, value)
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(*info->fprintf_func) (info->stream, "%ld", value);
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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}
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}
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}
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static void
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static void
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print_operand_bitnum (info, value)
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print_operand_bitnum (info, value)
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@ -133,7 +128,6 @@ print_operand_bitnum (info, value)
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(*info->fprintf_func) (info->stream, "%ld", bitnum);
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(*info->fprintf_func) (info->stream, "%ld", bitnum);
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}
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}
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}
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}
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/* Print the operand as directed by the flags. */
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/* Print the operand as directed by the flags. */
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@ -194,16 +188,15 @@ print_operand (info, value, insn, operand, memaddr)
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print_operand_integer (info, value);
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print_operand_integer (info, value);
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}
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}
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/* If this is a scaled operand, then print the modifier */
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/* If this is a scaled operand, then print the modifier. */
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if (R_SCALED (insn, operand))
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if (R_SCALED (insn, operand))
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{
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{
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(*info->fprintf_func) (info->stream, ":s");
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(*info->fprintf_func) (info->stream, ":s");
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}
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}
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}
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}
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/* We have chosen an opcode table entry */
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/* We have chosen an opcode table entry. */
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static int
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static int
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print_one_instruction (info, memaddr, insn, opcode)
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print_one_instruction (info, memaddr, insn, opcode)
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@ -277,14 +270,12 @@ print_one_instruction (info, memaddr, insn, opcode)
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}
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}
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return (length);
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return (length);
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}
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}
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/* There are no specific bits that tell us for certain whether a vector
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/* There are no specific bits that tell us for certain whether a vector
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instruction opcode contains one or two instructions. However since
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instruction opcode contains one or two instructions. However since
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a destination register of r0 is illegal, we can check for nonzero
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a destination register of r0 is illegal, we can check for nonzero
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values in both destination register fields. Only opcodes that have
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values in both destination register fields. Only opcodes that have
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two valid instructions will have non-zero in both */
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two valid instructions will have non-zero in both. */
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#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
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#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
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@ -316,7 +307,7 @@ print_instruction (info, memaddr, insn, vec_opcode)
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if (opcode == opcode_end)
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if (opcode == opcode_end)
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{
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{
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/* No match found, just print the bits as a .word directive */
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/* No match found, just print the bits as a .word directive. */
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(*info->fprintf_func) (info->stream, ".word %#08lx", insn);
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(*info->fprintf_func) (info->stream, ".word %#08lx", insn);
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}
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}
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else
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else
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@ -348,7 +339,7 @@ fill_instruction (info, memaddr, insnp)
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bfd_byte buffer[4];
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bfd_byte buffer[4];
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int status;
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int status;
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/* Get the bits for the next 32 bit word and put in buffer */
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/* Get the bits for the next 32 bit word and put in buffer. */
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status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
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status = (*info->read_memory_func) (memaddr + length, buffer, 4, info);
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if (status != 0)
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if (status != 0)
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@ -371,12 +362,11 @@ fill_instruction (info, memaddr, insnp)
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}
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}
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else
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else
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{
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{
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/* FIXME: Should probably just default to one or the other */
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/* FIXME: Should probably just default to one or the other. */
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abort ();
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abort ();
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}
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}
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return (0);
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return (0);
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}
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}
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int
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int
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print_insn_tic80 (memaddr, info)
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print_insn_tic80 (memaddr, info)
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