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* gdb.arch/altivec-regs.exp (decimal_vector): Adjust for output

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format changes.
This commit is contained in:
Ulrich Weigand
2007-10-21 12:24:34 +00:00
parent 430ebac964
commit c641edccb5
2 changed files with 7 additions and 2 deletions
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5
gdb/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2007-10-21 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* gdb.arch/altivec-regs.exp (decimal_vector): Adjust for output
format changes.
2007-10-18 Michael Snyder <msnyder@specifix.com>
* gdb.base/dbx.exp: Add missing "-re " operator.

4
gdb/testsuite/gdb.arch/altivec-regs.exp
View File

@ -124,9 +124,9 @@ gdb_test "info reg vscr" "vscr.*0x1\t1" "info reg vscr"
# the way gdb works.
if {$endianness == "big"} {
set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001'.."
set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
} else {
set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0'.."
set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0.."
}
for {set i 0} {$i < 32} {incr i 1} {