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mostly whitespace/comment changes

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This commit is contained in:
Ken Raeburn
1992-12-03 23:52:26 +00:00
parent 082e9570f1
commit c5dd66a13a
2 changed files with 72 additions and 81 deletions
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46
gas/config/tc-i386.c
View File

@ -779,6 +779,7 @@ md_assemble (line)
/* Now we've parsed the opcode into a set of templates, and have the /* Now we've parsed the opcode into a set of templates, and have the
operands at hand. operands at hand.
Next, we find a template that matches the given insn, Next, we find a template that matches the given insn,
making sure the overlap of the given operands types is consistent making sure the overlap of the given operands types is consistent
with the template operand types. */ with the template operand types. */
@ -996,20 +997,20 @@ md_assemble (line)
t->base_opcode |= found_reverse_match; t->base_opcode |= found_reverse_match;
} }
/* /* The imul $imm, %reg instruction is converted into
The imul $imm, %reg instruction is converted into
imul $imm, %reg, %reg. */ imul $imm, %reg, %reg. */
if (t->opcode_modifier & imulKludge) if (t->opcode_modifier & imulKludge)
{ {
i.regs[2] = i.regs[1]; /* Pretend we saw the 3 operand case. */ /* Pretend we saw the 3 operand case. */
i.regs[2] = i.regs[1];
i.reg_operands = 2; i.reg_operands = 2;
} }
/* Certain instructions expect the destination to be in the i.rm.reg /* Certain instructions expect the destination to be in the i.rm.reg
field. This is by far the exceptional case. For these instructions, field. This is by far the exceptional case. For these
if the source operand is a register, we must reverse the i.rm.reg instructions, if the source operand is a register, we must reverse
and i.rm.regmem fields. We accomplish this by faking that the the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
two register operands were given in the reverse order. */ that the two register operands were given in the reverse order. */
if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2) if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
{ {
unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1; unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
@ -1067,9 +1068,10 @@ md_assemble (line)
source = (i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 : 1; source = (i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 : 1;
dest = source + 1; dest = source + 1;
i.rm.mode = 3; i.rm.mode = 3;
/* We must be careful to make sure that all segment/control/test/ /* We must be careful to make sure that all
debug registers go into the i.rm.reg field (despite the whether segment/control/test/debug registers go into the i.rm.reg
they are source or destination operands). */ field (despite the whether they are source or destination
operands). */
if (i.regs[dest]->reg_type & (SReg2 | SReg3 | Control | Debug | Test)) if (i.regs[dest]->reg_type & (SReg2 | SReg3 | Control | Debug | Test))
{ {
i.rm.reg = i.regs[dest]->reg_num; i.rm.reg = i.regs[dest]->reg_num;
@ -1167,8 +1169,8 @@ md_assemble (line)
} }
if (fake_zero_displacement) if (fake_zero_displacement)
{ {
/* Fakes a zero displacement assuming that i.types[o] holds /* Fakes a zero displacement assuming that i.types[o]
the correct displacement size. */ holds the correct displacement size. */
exp = &disp_expressions[i.disp_operands++]; exp = &disp_expressions[i.disp_operands++];
i.disps[o] = exp; i.disps[o] = exp;
exp->X_seg = SEG_ABSOLUTE; exp->X_seg = SEG_ABSOLUTE;
@ -1209,24 +1211,24 @@ md_assemble (line)
} }
/* Fill in i.rm.reg or i.rm.regmem field with register operand /* Fill in i.rm.reg or i.rm.regmem field with register operand
(if any) based on t->extension_opcode. Again, we must be careful (if any) based on t->extension_opcode. Again, we must be
to make sure that segment/control/debug/test registers are coded careful to make sure that segment/control/debug/test
into the i.rm.reg field. */ registers are coded into the i.rm.reg field. */
if (i.reg_operands) if (i.reg_operands)
{ {
unsigned int o = unsigned int o =
(i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 : (i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 :
(i.types[1] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 1 : 2; (i.types[1] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 1 : 2;
/* If there is an extension opcode to put here, the register number /* If there is an extension opcode to put here, the
must be put into the regmem field. */ register number must be put into the regmem field. */
if (t->extension_opcode != None) if (t->extension_opcode != None)
i.rm.regmem = i.regs[o]->reg_num; i.rm.regmem = i.regs[o]->reg_num;
else else
i.rm.reg = i.regs[o]->reg_num; i.rm.reg = i.regs[o]->reg_num;
/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
we must set it to 3 to indicate this is a register operand we must set it to 3 to indicate this is a register
int the regmem field */ operand int the regmem field */
if (!i.mem_operands) if (!i.mem_operands)
i.rm.mode = 3; i.rm.mode = 3;
} }
@ -2457,10 +2459,4 @@ tc_coff_fix2rtype (fixP)
#endif #endif
/*
* Local Variables:
* comment-column: 0
* End:
*/
/* end of tc-i386.c */ /* end of tc-i386.c */

13
gas/config/te-ic960.h
View File

@ -31,16 +31,11 @@
#endif /* CROSS_COMPILE */ #endif /* CROSS_COMPILE */
#define OBJ_COFF_OMIT_OPTIONAL_HEADER #define OBJ_COFF_OMIT_OPTIONAL_HEADER
#define LOCAL_LABEL(name) ( (name[0] =='L') \ #define LOCAL_LABEL(name) ((name[0] =='L') \
|| (name[0] =='.' \ || (name[0] =='.' \
&& (name[1]=='C' || name[1]=='I' || name[1]=='.'))) && (name[1]=='C' \
|| name[1]=='I' \
|| name[1]=='.')))
#include "obj-format.h" #include "obj-format.h"
/*
* Local Variables:
* comment-column: 0
* fill-column: 131
* End:
*/
/* end of te-ic960.h */ /* end of te-ic960.h */